Abstract: A host system includes a host device, a host buffer memory, and storage device. The host device includes a plurality of cores. The host buffer memory is configured to store a first command queue and a first map table, wherein each of the first command queue and the first map table corresponds to a first core of the cores. The storage device is configured to perform an input/output virtualization operation using the first core as a virtual core. The storage device uses the first command queue and the first map table during the input/output virtualization operation using the first core.

Abstract: A semiconductor device includes a plurality of circuits, a general bus configured to be connected to each of the plurality of circuits and to provide a general channel among the plurality of circuits, and a designated bus configured to be connected to a subgroup of circuits from among the plurality of circuits and to provide a designated channel among the subgroup of circuits.

Abstract: A semiconductor device includes a plurality of circuits, a general bus configured to be connected to each of the plurality of circuits and to provide a general channel among the plurality of circuits, and a designated bus configured to be connected to a subgroup of circuits from among the plurality of circuits and to provide a designated channel among the subgroup of circuits.

Abstract: In a method of operating a device, signals associated with wakeup of the device are detected using a first physical layer among a plurality of physical layers, and a detection signal is generated based on the detected signals. The detection signal is transmitted directly to a power management circuit. The first physical layer is included in logical lane #0 or physical lane #0.

Abstract: A host system includes a host device, a host buffer memory, and storage device. The host device includes a plurality of cores. The host buffer memory is configured to store a first command queue and a first map table, wherein each of the first command queue and the first map table corresponds to a first core of the cores. The storage device is configured to perform an input/output virtualization operation using the first core as a virtual core. The storage device uses the first command queue and the first map table during the input/output virtualization operation using the first core.

Abstract: A storage device which includes a user area of a memory cell array; a buffer area configured to temporarily store compressed data to be written into the user area; and compressed data management logic configured to control the user area and the buffer area such that compressed data stored in the buffer area is written into the user area. The compressed data management logic manages compressed data to be written into the user area by an ECC block unit rather than by a page-size unit.

Abstract: A solid state drive (SSD) interface controller includes a host interface, first and second command interfaces, and an interface information storage unit. The interface information storage unit is configured to store information for determining activation or deactivation of each of the first and second command interfaces, and a capacity allocated to each of the first and second command interfaces. The interface information storage unit may comprise first and second registers storing interface information, which may be changed in response to an extension ROM BIOS executed during a booting operation. The command interfaces may be configured to communicate using interface protocols such as SATA, SATA express, or nonvolatile express. An interface power management unit may cut power to an interface when deactivated based on the stored interface information.

Abstract: In a method of operating a device, signals associated with wakeup of the device are detected using a first physical layer among a plurality of physical layers, and a detection signal is generated based on the detected signals. The detection signal is transmitted directly to a power management circuit. The first physical layer is included in logical lane #0 or physical lane #0.

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Abstract: At least one example embodiment discloses a method of compressing data in a storage device. The method includes determining a codeword length of a symbol using a first table indicating a relationship between a number of occurrences of the symbol in received data and the codeword length, determining a codeword having the codeword length for the symbol, and generating compressed data of the received data, the generating including converting the symbol into the codeword.

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Abstract: A solid state drive (SSD) interface controller includes a host interface, first and second command interfaces, and an interface storage unit. The host interface is configured to communicate data with a host device. The first command interface is configured to communicate data between the host interface and an SSD, and the second command interface is configured to communicate data between the host interface and the SSD independently of the first command interface. The interface information storage unit is configured to store information for determining activation or deactivation of each of the first and second command interfaces, and a capacity allocated to each of the first and second command interfaces.

Abstract: A storage device which includes a user area of a memory cell array; a buffer area configured to temporarily store compressed data to be written into the user area; and compressed data management logic configured to control the user area and the buffer area such that compressed data stored in the buffer area is written into the user area. The compressed data management logic manages compressed data to be written into the user area by an ECC block unit rather than by a page-size unit.

Abstract: Provided are a memory system and a method of driving the same. The method includes setting microcodes in a top control sequencer and multiple channel control sequencers, and executing the microcode set in the top control sequencer. The method may further include checking execution results of the microcode.

Abstract: At least one example embodiment discloses a method of compressing data in a storage device. The method includes determining a codeword length of a symbol using a first table indicating a relationship between a number of occurrences of the symbol in received data and the codeword length, determining a codeword having the codeword length for the symbol, and generating compressed data of the received data, the generating including converting the symbol into the codeword.

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.