Patents by Inventor Je-In Yu

Je-In Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240282724
    Abstract: An antenna-integrated high-frequency semiconductor package, including a substrate including a recess concave on a first surface and a first through-hole penetrating from the first surface to a second surface, a ground layer configured to cover the first surface of the substrate and the recess, a semiconductor chip mounted on the ground layer of the recess, an insulating layer configured to entirely cover the substrate, the ground layer, and the semiconductor chip, and a conductive layer formed on the insulating layer, the conductive layer including an electrode pattern connected to the semiconductor chip, an antenna formed on a second surface of the insulating layer, and a signal via configured to transmit an electrical signal between the electrode pattern and the antenna through a second through-hole formed in the first through-hole to penetrate from the first surface to the second surface of the insulating layer.
    Type: Application
    Filed: February 13, 2024
    Publication date: August 22, 2024
    Applicant: KOREA ELECTRONICS TECHNOLOGY INSTITUTE
    Inventors: Jong Min YOOK, Je In YU, Dong Su KIM
  • Patent number: 12014881
    Abstract: The present invention provides a method for manufacturing a high frequency capacitor, including preparing a substrate for formation of the capacitor, forming a dielectric layer at an upper surface of the substrate, forming an upper electrode at an upper surface of the dielectric layer, and removing a portion of a lower surface of the substrate, to expose a lower surface of the dielectric layer, and forming a lower electrode at the lower surface of the dielectric layer. The high frequency capacitor includes a dielectric layer having a uniform surface, a thick upper electrode, and a thick lower electrode and, as such, exhibits high quality factor (Q) even at a high frequency.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: June 18, 2024
    Assignee: KOREA ELECTRONICS TECHNOLOGY INSTITUTE
    Inventors: Jong Min Yook, Je In Yu, Jun Chul Kim, Dong Su Kim
  • Publication number: 20230145380
    Abstract: A waveguide package and a method for manufacturing the same are disclosed. The waveguide package includes a package structure including a waveguide opened toward one side surface of a substrate, a semiconductor chip mounted on one surface of the package structure and configured to output an electrical signal to the waveguide. Since an interior of the waveguide is filled with air, electrical loss of the waveguide is minimized The cavity is formed by processing the substrate made of photosensitive glass. Accordingly, the waveguide may be accurately formed. An electronic circuit may also be formed at the waveguide package. Accordingly, it may be possible to provide a waveguide package enhanced in degree of integration.
    Type: Application
    Filed: November 7, 2022
    Publication date: May 11, 2023
    Inventors: Jong Min YOOK, Je In YU, Dong Su KIM
  • Publication number: 20230107554
    Abstract: A semiconductor package including a semiconductor chip, and a package structure configured to accommodate the semiconductor chip, and a manufacturing method thereof are disclosed. The package structure includes a substrate having one surface and the other surface opposite to the one surface, at least one conductive via extending through one surface and the other surface of the substrate, a wiring layer formed at one surface of the substrate, to transmit an electrical signal, a chip accommodating portion formed through removal of a portion of the substrate from the other surface toward the one surface, and a contact pad connected to the wiring layer and formed to be exposed through the chip accommodating portion. The semiconductor chip is inserted into the chip accommodating portion and is connected to the contact pad. Since the semiconductor chip is mounted after formation of the package structure, yield of the semiconductor package increases.
    Type: Application
    Filed: August 31, 2022
    Publication date: April 6, 2023
    Inventors: Jong Min YOOK, Je In YU, Dong Su KIM
  • Publication number: 20220328253
    Abstract: The present invention provides a method for manufacturing a high frequency capacitor, including preparing a substrate for formation of the capacitor, forming a dielectric layer at an upper surface of the substrate, forming an upper electrode at an upper surface of the dielectric layer, and removing a portion of a lower surface of the substrate, to expose a lower surface of the dielectric layer, and forming a lower electrode at the lower surface of the dielectric layer. The high frequency capacitor includes a dielectric layer having a uniform surface, a thick upper electrode, and a thick lower electrode and, as such, exhibits high quality factor (Q) even at a high frequency.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 13, 2022
    Inventors: Jong Min YOOK, Je In YU, Jun Chul KIM, Dong Su KIM
  • Publication number: 20100326707
    Abstract: A package substrate, a manufacturing method thereof, a base package module, and a multi-layered package module having package substrates laminated on upper and lower portions of a base package module are provided. The base package module includes a base metal substrate, a first metal oxide layer that is formed on the base metal substrate to have a cavity therein, a device that is mounted in the cavity on the base metal substrate and insulated by the first metal oxide layer formed on a sidewall in the cavity, and a conductor that is connected to the device and a wiring pad formed on the first metal oxide layer on the base metal substrate. The package substrate includes a wiring pad, a conductor line, a second metal oxide layer having an opening that exposes a device, and a via that is connected to the wiring pad through a connection pad in the second metal oxide layer.
    Type: Application
    Filed: September 18, 2007
    Publication date: December 30, 2010
    Applicants: Wavenics Inc., Korea Advanced Institute of Science and Technology
    Inventors: Young-Se Kwon, Kyoung-Min Kim, Je-In Yu