Abstract: The present invention relates to a novel heterocyclic compound and a composition, for preventing or treating a cancer, an autoimmune disease, and an inflammatory disease, comprising same. The novel heterocyclic compound of the present invention is a bifunctional compound having a Bruton's tyrosine kinase (BTK) degradation function via a ubiquitin proteasome pathway, and may be utilized as a composition for preventing or treating a cancer, an autoimmune disease, and Parkinson's disease.

Abstract: The present disclosure provides a substituted piperidine compound of Chemical Formula 1, or a pharmaceutically acceptable salt thereof having activity of degrading androgen receptor (AR). The present disclosure also provides a composition comprising such a substituted piperidine compound or a pharmaceutically acceptable salt thereof. The present disclosure also provides a medical use of a substituted piperidine compound according to the present disclosure, a salt thereof, and a composition comprising the same for the treatment or prophylaxis of AR-related diseases. The present disclosure also provides a method for treating or preventing an AR-related disease comprising administering to a subject in need thereof an effective amount of a substituted piperidine compound according to the present disclosure, a salt thereof, or a composition comprising the same.

Abstract: A cooling apparatus for a power module including a plurality of cooling modules provided to be in contact with each of both surfaces of the power module, in which the cooling module includes a manifold cover provided with a plurality of guide walls extending in a first direction in a state of being spaced apart from each other and a pin plate having one surface being in contact with the power module and having a plurality of pins extending in a second direction crossing the first direction formed on the other surface thereof.

Abstract: The inventive concept provides a substrate treating apparatus.

Abstract: A battery can include an electrode assembly including a first electrode, a second electrode, and a separator between the first electrode and the second electrode. The first electrode can have a pair of first sides and a pair of second sides extending between the pair of first sides, a first portion including an active material extending between the pair of first sides, and a second portion extending between the pair of first sides and exposed beyond the separator along a winding direction. The battery can further include a battery housing having a first opening at a first end and a second end with a second opening opposite the first end, a first current collector including a support portion positioned on the electrode assembly, and a housing cover which seals the first opening.

Abstract: The present disclosure provides a substituted piperidine compound of Chemical Formula 1, wherein X is CR3, or a pharmaceutically acceptable salt thereof having activity of degrading androgen receptor (AR). The present disclosure also provides a composition comprising such a substituted piperidine compound or a pharmaceutically acceptable salt thereof. The present disclosure also provides a medical use of a substituted piperidine compound according to the present disclosure, a salt thereof, and a composition comprising the same for the treatment or prophylaxis of AR-related diseases. The present disclosure also provides a method for treating or preventing an AR-related disease comprising administering to a subject in need thereof an effective amount of a substituted piperidine compound according to the present disclosure, a salt thereof, or a composition comprising the same.

Abstract: The present application can provide a curable composition capable of securing processability due to excellent blending properties with a filler while having little viscosity change with time and for forming a cured product having excellent electrical insulation performance, and can provide a device comprising, between an exothermic element and a cooling region, a cured product of a tow-component curable composition including the curable composition in thermal contact with both.

Abstract: The present invention relates to a novel heterocyclic compound and a composition, for preventing or treating a cancer, an autoimmune disease, and an inflammatory disease, comprising same. The novel heterocyclic compound of the present invention is a bifunctional compound having a Bruton's tyrosine kinase (BTK) degradation function via a ubiquitin proteasome pathway, and may be utilized as a composition for preventing or treating a cancer, an autoimmune disease, and Parkinson's disease.

Abstract: A semiconductor memory device comprises a substrate, first and second lower electrode groups on the substrate and including a plurality of first and second lower electrodes, respectively, and first and second support patterns on side walls of and connecting each of the first and second lower electrodes, respectively. The first lower electrodes include a first center lower electrode arranged within a hexagonal shape defined by first edge lower electrodes. The second lower electrodes include a second center lower electrode arranged within a hexagonal shape defined by second edge lower electrodes. The first center lower electrode is spaced apart from each of the first edge lower electrodes in different first to third directions. The first support pattern is immediately adjacent to the second support pattern. The first center lower electrode is spaced apart from the second center lower electrode in a fourth direction different from the first to third directions.

Abstract: A semiconductor memory device comprises a substrate, first and second lower electrode groups on the substrate and including a plurality of first and second lower electrodes, respectively, and first and second support patterns on side walls of and connecting each of the first and second lower electrodes, respectively. The first lower electrodes include a first center lower electrode arranged within a hexagonal shape defined by first edge lower electrodes. The second lower electrodes include a second center lower electrode arranged within a hexagonal shape defined by second edge lower electrodes. The first center lower electrode is spaced apart from each of the first edge lower electrodes in different first to third directions. The first support pattern is immediately adjacent to the second support pattern. The first center lower electrode is spaced apart from the second center lower electrode in a fourth direction different from the first to third directions.

Abstract: A method of forming a semiconductor device includes forming first sacrificial patterns on a lower structure, forming first remaining mask layers having a “U” shape between the first sacrificial patterns to be in contact with the first sacrificial patterns, forming first remaining mask patterns by pattering the first remaining mask layers, each of the first remaining mask patterns including a horizontal portion, parallel to an upper surface of the lower structure, and a vertical portion, perpendicular to the upper surface of the lower structure, forming second mask patterns spaced apart from the vertical portions of the first remaining mask patterns, removing the first sacrificial patterns remaining after forming the second mask patterns, and forming first mask patterns by etching the horizontal portions of the first remaining mask patterns.

Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.

Abstract: A semiconductor memory device comprises a substrate, first and second lower electrode groups on the substrate and including a plurality of first and second lower electrodes, respectively, and first and second support patterns on side walls of and connecting each of the first and second lower electrodes, respectively. The first lower electrodes include a first center lower electrode arranged within a hexagonal shape defined by first edge lower electrodes. The second lower electrodes include a second center lower electrode arranged within a hexagonal shape defined by second edge lower electrodes. The first center lower electrode is spaced apart from each of the first edge lower electrodes in different first to third directions. The first support pattern is immediately adjacent to the second support pattern. The first center lower electrode is spaced apart from the second center lower electrode in a fourth direction different from the first to third directions.

Abstract: A method includes forming hard mask patterns by depositing a support mask layer, a polycrystalline silicon layer, and a hard mask layer on a substrate and etching the hard mask layer, forming pre-polycrystalline silicon patterns by etching the polycrystalline silicon layer using the hard mask patterns as an etch mask, oxidizing side surfaces of the pre-polycrystalline silicon patterns to form polycrystalline silicon patterns and a silicon oxide layer, forming spacer patterns covering sides of the silicon oxide layer, forming a sacrificial layer on a top surface of the support mask layer to cover the silicon oxide layer and the spacer patterns, etching the sacrificial layer and the silicon oxide layer, forming support mask patterns by etching the support mask layer using the polycrystalline silicon patterns and the spacer patterns as an etch mask, and forming activation pins by etching the substrate using the support mask patterns as an etch mask.

Abstract: An integrated circuit device includes a substrate having a first region and a second region separated from each other along a direction parallel to an upper surface of the substrate. An interface device isolation layer fills an interface trench in an interface region between the first region and the second region and defines a portion of a first active area positioned in the first region and a portion of a second active area positioned in the second region. An insulation pattern extends from the first region to an upper portion of the interface device isolation layer. The insulation pattern covers the first active area and at least a portion of the interface device isolation layer. The insulation pattern defines an undercut area on an upper surface of the interface device isolation layer. A buried pattern substantially fills the undercut region.

Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.

Abstract: An integrated circuit device includes a gate stack structure on a base layer, the gate stack structure having a gate insulating layer with a first dielectric layer on the base layer and having first relative permittivity, and a gate structure on the gate insulating layer, and a gate spacer structure on opposite side walls of the gate stack structure and on the base layer, the gate spacer structure including a buried dielectric layer buried in a recess hole of the gate insulating layer at a lower portion of the gate spacer structure on the base layer, and the buried dielectric layer including a same material as the first dielectric layer.

Abstract: A method includes forming hard mask patterns by depositing a support mask layer, a polycrystalline silicon layer, and a hard mask layer on a substrate and etching the hard mask layer, forming pre-polycrystalline silicon patterns by etching the polycrystalline silicon layer using the hard mask patterns as an etch mask, oxidizing side surfaces of the pre-polycrystalline silicon patterns to form polycrystalline silicon patterns and a silicon oxide layer, forming spacer patterns covering sides of the silicon oxide layer, forming a sacrificial layer on a top surface of the support mask layer to cover the silicon oxide layer and the spacer patterns, etching the sacrificial layer and the silicon oxide layer, forming support mask patterns by etching the support mask layer using the polycrystalline silicon patterns and the spacer patterns as an etch mask, and forming activation pins by etching the substrate using the support mask patterns as an etch mask.