Patents by Inventor JE-MIN RYU

JE-MIN RYU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12161722
    Abstract: The present invention relates to a novel heterocyclic compound and a composition, for preventing or treating a cancer, an autoimmune disease, and an inflammatory disease, comprising same. The novel heterocyclic compound of the present invention is a bifunctional compound having a Bruton's tyrosine kinase (BTK) degradation function via a ubiquitin proteasome pathway, and may be utilized as a composition for preventing or treating a cancer, an autoimmune disease, and Parkinson's disease.
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: December 10, 2024
    Assignees: KOREA RESEARCH INSTITUTE OF CHEMICAL TECHNOLOGY, UBIX THERAPEUTICS, INC.
    Inventors: Pil Ho Kim, Sung Yun Cho, Jae Du Ha, Chi Hoon Park, Jong Yeon Hwang, Hyun Jin Kim, Song Hee Lee, Ye Seul Lim, Han Wool Kim, Sun Mi Yoo, Beom Seon Suh, Ji Youn Park, Je Ho Ryu, Jung Min Ahn, Hee Jung Moon, Ho Hyun Lee
  • Publication number: 20240383877
    Abstract: The present disclosure provides a substituted piperidine compound of Chemical Formula 1, or a pharmaceutically acceptable salt thereof having activity of degrading androgen receptor (AR). The present disclosure also provides a composition comprising such a substituted piperidine compound or a pharmaceutically acceptable salt thereof. The present disclosure also provides a medical use of a substituted piperidine compound according to the present disclosure, a salt thereof, and a composition comprising the same for the treatment or prophylaxis of AR-related diseases. The present disclosure also provides a method for treating or preventing an AR-related disease comprising administering to a subject in need thereof an effective amount of a substituted piperidine compound according to the present disclosure, a salt thereof, or a composition comprising the same.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 21, 2024
    Inventors: Song Hee LEE, Je Ho RYU, Jung Min AHN, Yu Ri CHOI, Ho Hyun LEE, Mi Young JANG, Yae Jin WOO, Hanwool KIM, Ji Young KIM, Ji Youn PARK
  • Patent number: 12136707
    Abstract: A battery can include an electrode assembly including a first electrode, a second electrode, and a separator between the first electrode and the second electrode. The first electrode can have a pair of first sides and a pair of second sides extending between the pair of first sides, a first portion including an active material extending between the pair of first sides, and a second portion extending between the pair of first sides and exposed beyond the separator along a winding direction. The battery can further include a battery housing having a first opening at a first end and a second end with a second opening opposite the first end, a first current collector including a support portion positioned on the electrode assembly, and a housing cover which seals the first opening.
    Type: Grant
    Filed: April 7, 2023
    Date of Patent: November 5, 2024
    Assignee: LG ENERGY SOLUTION, LTD.
    Inventors: Jae-Won Lim, Hak-Kyun Kim, Je-Jun Lee, Ji-Min Jung, Su-Ji Choi, Kwang-Su Hwangbo, Do-Gyun Kim, Geon-Woo Min, Hae-Jin Lim, Min-Ki Jo, Jae-Woong Kim, Jong-Sik Park, Yu-Sung Choe, Byoung-Gu Lee, Duk-Hyun Ryu, Kwan-Hee Lee, Jae-Eun Lee, Bo-Hyun Kang, Jin-Hak Kong, Soon-O Lee, Kyu-Hyun Choi, Pil-Kyu Park
  • Patent number: 12122763
    Abstract: The present disclosure provides a substituted piperidine compound of Chemical Formula 1, wherein X is CR3, or a pharmaceutically acceptable salt thereof having activity of degrading androgen receptor (AR). The present disclosure also provides a composition comprising such a substituted piperidine compound or a pharmaceutically acceptable salt thereof. The present disclosure also provides a medical use of a substituted piperidine compound according to the present disclosure, a salt thereof, and a composition comprising the same for the treatment or prophylaxis of AR-related diseases. The present disclosure also provides a method for treating or preventing an AR-related disease comprising administering to a subject in need thereof an effective amount of a substituted piperidine compound according to the present disclosure, a salt thereof, or a composition comprising the same.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: October 22, 2024
    Assignee: UBIX THERAPEUTICS, INC.
    Inventors: Song Hee Lee, Je Ho Ryu, Jung Min Ahn, Yu Ri Choi, Ho Hyun Lee, Mi Young Jang, Yae Jin Woo, Hanwool Kim, Ji Young Kim, Ji Youn Park
  • Publication number: 20240285778
    Abstract: The present invention relates to a novel heterocyclic compound and a composition, for preventing or treating a cancer, an autoimmune disease, and an inflammatory disease, comprising same. The novel heterocyclic compound of the present invention is a bifunctional compound having a Bruton's tyrosine kinase (BTK) degradation function via a ubiquitin proteasome pathway, and may be utilized as a composition for preventing or treating a cancer, an autoimmune disease, and Parkinson's disease.
    Type: Application
    Filed: June 24, 2022
    Publication date: August 29, 2024
    Applicants: KOREA RESEARCH INSTITUTE OF CHEMICAL TECHNOLOGY, UBIX THERAPEUTICS, INC.
    Inventors: Pil Ho KIM, Sung Yun CHO, Jae Du HA, Chi Hoon PARK, Jong Yeon HWANG, Hyun Jin KIM, Song Hee LEE, Ye Seul LIM, Han Wool KIM, Sun Mi YOO, Beom Seon SUH, Ji Youn PARK, Je Ho RYU, Jung Min AHN, Hee Jung MOON, Ho Hyun LEE
  • Publication number: 20230410891
    Abstract: A method for using a high bandwidth memory controller includes providing a clock signal having a first clock frequency, providing a write strobe signal having a second clock frequency, providing a write command/address signal based on the clock signal, and providing a write data signal based on the write strobe signal. The first clock frequency is half of the second clock frequency, the write strobe signal has two cycles of pre-amble before the write data signal, and the write strobe signal has two cycles of post-amble after the write data signal.
    Type: Application
    Filed: August 30, 2023
    Publication date: December 21, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byongmo MOON, Jihye KIM, Je Min RYU, Beomyong KIL, Sungoh AHN
  • Patent number: 11836097
    Abstract: A memory device includes a first channel including a first cell array and communicating with a memory controller through a first path, a second channel including a second cell array and communicating with the memory controller through a second path, and an assignment control circuit configured to monitor memory usage of the first and second channels and further assign a storage space of a portion of the second cell array to the first channel when the memory usage of the first cell array exceeds a threshold value. Access to the storage space of the portion of the second cell array assigned to the first channel is performed through the first path.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: December 5, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Won Park, Je-Min Ryu, Sang-Hoon Shin, Jae-Hoon Jung
  • Patent number: 11769547
    Abstract: A method for using a high bandwidth memory controller includes providing a clock signal having a first clock frequency, providing a write strobe signal having a second clock frequency, providing a write command/address signal based on the clock signal, and providing a write data signal based on the write strobe signal. The first clock frequency is half of the second clock frequency, the write strobe signal has two cycles of pre-amble before the write data signal, and the write strobe signal has two cycles of post-amble after the write data signal.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: September 26, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byongmo Moon, Jihye Kim, Je Min Ryu, Beomyong Kil, Sungoh Ahn
  • Publication number: 20220310154
    Abstract: A method for using a high bandwidth memory controller includes providing a clock signal having a first clock frequency, providing a write strobe signal having a second clock frequency, providing a write command/address signal based on the clock signal, and providing a write data signal based on the write strobe signal. The first clock frequency is half of the second clock frequency, the write strobe signal has two cycles of pre-amble before the write data signal, and the write strobe signal has two cycles of post-amble after the write data signal.
    Type: Application
    Filed: March 2, 2022
    Publication date: September 29, 2022
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byongmo MOON, Jihye KIM, Je Min RYU, Beomyong KIL, Sungoh AHN
  • Patent number: 11295808
    Abstract: A memory device includes a control logic circuit, a write data strobe signal divider, a data transceiver, and a memory cell array. The control logic circuit generates a reset signal before a write data strobe signal provided from a memory controller starts to toggle. The write data strobe signal divider generates internal write data strobe signals that toggle depending on toggling of the write data strobe signal, the internal write data strobe signals toggling with different phases, respectively. The control logic circuit initializes the internal write data strobe signals to given values in response to the reset signal. The data transceiver receives write data provided from the memory controller based on the internal write data strobe signals. The memory cell array stores the received write data.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: April 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byongmo Moon, Jihye Kim, Je Min Ryu, Beomyong Kil, Sungoh Ahn
  • Patent number: 11239210
    Abstract: A semiconductor die may include a first delay circuit formed on a substrate and configured to delay a test signal, the first delay circuit including first delay stages connected in series, a second delay circuit formed on the substrate and configured to delay the test signal, the second delay circuit including second delay stages connected in series, at least one through silicon via connected to at least one output terminal of output terminals of the first delay stages, the at least one through silicon via penetrating through the substrate, and a load determinator configured to compare a first delay signal output from one of the first delay stages with a second delay signal output from one of the second delay stages and determine a load of the at least one through silicon via.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: February 1, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: SeungHan Woo, Je Min Ryu, Reum Oh, Moonhee Oh, BumSuk Lee
  • Publication number: 20210232513
    Abstract: A memory device includes a first channel including a first cell array and communicating with a memory controller through a first path, a second channel including a second cell array and communicating with the memory controller through a second path, and an assignment control circuit configured to monitor memory usage of the first and second channels and further assign a storage space of a portion of the second cell array to the first channel when the memory usage of the first cell array exceeds a threshold value. Access to the storage space of the portion of the second cell array assigned to the first channel is performed through the first path.
    Type: Application
    Filed: April 13, 2021
    Publication date: July 29, 2021
    Inventors: JAE-WON PARK, Je-Min Ryu, Sang-Hoon Shin, Jae-Hoon Jung
  • Publication number: 20210225426
    Abstract: A memory device includes a control logic circuit, a write data strobe signal divider, a data transceiver, and a memory cell array. The control logic circuit generates a reset signal before a write data strobe signal provided from a memory controller starts to toggle. The write data strobe signal divider generates internal write data strobe signals that toggle depending on toggling of the write data strobe signal, the internal write data strobe signals toggling with different phases, respectively. The control logic circuit initializes the internal write data strobe signals to given values in response to the reset signal. The data transceiver receives write data provided from the memory controller based on the internal write data strobe signals. The memory cell array stores the received write data.
    Type: Application
    Filed: October 29, 2020
    Publication date: July 22, 2021
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byongmo MOON, Jihye Kim, Je Min Ryu, Beomyong Kil, Sungoh Ahn
  • Patent number: 11010316
    Abstract: A memory device includes a first channel including a first cell array and communicating with a memory controller through a first path, a second channel including a second cell array and communicating with the memory controller through a second path, and an assignment control circuit configured to monitor memory usage of the first and second channels and further assign a storage space of a portion of the second cell array to the first channel when the memory usage of the first cell array exceeds a threshold value. Access to the storage space of the portion of the second cell array assigned to the first channel is performed through the first path.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: May 18, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Won Park, Je-Min Ryu, Sang-Hoon Shin, Jae-Hoon Jung
  • Publication number: 20210104498
    Abstract: A semiconductor die may include a first delay circuit formed on a substrate and configured to delay a test signal, the first delay circuit including first delay stages connected in series, a second delay circuit formed on the substrate and configured to delay the test signal, the second delay circuit including second delay stages connected in series, at least one through silicon via connected to at least one output terminal of output terminals of the first delay stages, the at least one through silicon via penetrating through the substrate, and a load determinator configured to compare a first delay signal output from one of the first delay stages with a second delay signal output from one of the second delay stages and determine a load of the at least one through silicon via.
    Type: Application
    Filed: December 17, 2020
    Publication date: April 8, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: SeungHan WOO, Je Min RYU, Reum OH, Moonhee OH, BumSuk LEE
  • Patent number: 10916525
    Abstract: A semiconductor die may include a first delay circuit formed on a substrate and configured to delay a test signal, the first delay circuit including first delay stages connected in series, a second delay circuit formed on the substrate and configured to delay the test signal, the second delay circuit including second delay stages connected in series, at least one through silicon via connected to at least one output terminal of output terminals of the first delay stages, the at least one through silicon via penetrating through the substrate, and a load determinator configured to compare a first delay signal output from one of the first delay stages with a second delay signal output from one of the second delay stages and determine a load of the at least one through silicon via.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: February 9, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: SeungHan Woo, Je Min Ryu, Reum Oh, Moonhee Oh, BumSuk Lee
  • Patent number: 10768824
    Abstract: A stacked memory includes a logic semiconductor die, a plurality of memory semiconductor dies stacked with the logic semiconductor die, a plurality of through-silicon vias (TSVs) electrically connecting the logic semiconductor die and the memory semiconductor dies, a global processor disposed in the logic semiconductor die and configured to perform a global sub process corresponding to a portion of a data process, a plurality of local processors respectively disposed in the memory semiconductor dies and configured to perform local sub processes corresponding to other portions of the data process and a plurality of memory integrated circuits respectively disposed in the memory semiconductor dies and configured to store data associated with the data process.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: September 8, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hak-Soo Yu, Je-Min Ryu, Reum Oh, Pavan Kumar Kasibhatla, Seok-In Hong
  • Patent number: 10671464
    Abstract: A memory device includes a command decoder and a status circuit. The command decoder decodes a command. The status circuit sequentially stores operation information of the memory device determined based on the decoded command and outputs at least one of the sequentially stored operation information in response to an output control signal.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Moonhee Oh, Je Min Ryu, Reum Oh, Jaeyoun Youn
  • Patent number: 10592467
    Abstract: An operation method of a semiconductor memory device including a memory cell array and an internal processor configured to perform an internal processing operation includes receiving at the memory device a first mode indicator that indicates whether the memory device should operate in a processor mode or in a normal mode, receiving at the memory device processing information for the memory device, when the first mode indicator indicates that the memory device should operate in the processor mode, storing the processing information in a first memory cell region of the memory cell array, using the stored processing information to perform internal processing by the internal processor, and storing a result of the internal processing in the memory cell array.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: March 17, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Je Min Ryu, Reum Oh, Hak-Soo Yu
  • Patent number: 10468092
    Abstract: A memory device includes a memory cell array that includes a plurality of memory cell rows; and a refresh address generator configured to store flags respectively corresponding to the plurality of memory cell rows, generate refresh row addresses respectively corresponding to the plurality of memory cell rows by performing a count operation, and according to the flags, change a refresh period of the plurality of memory cell rows.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: November 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-ho Hyun, Kyo-min Sohn, Je-min Ryu, Ho-Seok Seol