Abstract: A method for manufacturing a secondary battery is provided. The method includes accommodating an electrode assembly in a battery case, injecting a first electrolyte composition into the battery case to impregnate the electrode assembly, injecting a second electrolyte composition into the battery case, and curing the second electrolyte composition, wherein an electrode tab is connected to the electrode assembly and protrudes to the outside of the electrode assembly, wherein the first electrolyte composition includes a 1-1st lithium salt containing at least one selected from the group consisting of lithium bis(fluorosulfonyl)imide (LiFSI) and lithium bis(trifluoromethanesulfonyl)imide (LiTFSI), and a first solvent, wherein the second electrolyte composition includes an oligomer and a second solvent and does not include lithium bis(fluorosulfonyl)imide (LiFSI) and lithium bis(trifluoromethanesulfonyl)imide (LiTFSI).

Abstract: A secondary battery including an electrode assembly, a gel polymer electrolyte, and a battery case accommodating the electrode assembly and the gel polymer electrolyte. The electrode assembly includes a plurality of electrodes and a plurality of separators, the plurality of electrodes are stacked in a vertical direction, and each of the plurality of separators is disposed between the stacked electrodes. The separator includes a porous substrate and a ceramic coating layer disposed on both sides of the porous substrate, and the ceramic coating layer contains inorganic particles and a binder, wherein the inorganic particles are included in an amount ranging from 92 wt % to less than 100 wt %, and the binder is included in an amount ranging from greater than 0 wt % to 8 wt %. The method of making the battery is also provided.

Abstract: The present invention relates to a novel heterocyclic compound and a composition, for preventing or treating a cancer, an autoimmune disease, and an inflammatory disease, comprising same. The novel heterocyclic compound of the present invention is a bifunctional compound having a Bruton's tyrosine kinase (BTK) degradation function via a ubiquitin proteasome pathway, and may be utilized as a composition for preventing or treating a cancer, an autoimmune disease, and Parkinson's disease.

Abstract: A secondary battery includes an electrode assembly including an electrode and a separator which are alternately stacked; a gel polymer electrolyte; and a battery case accommodating the electrode assembly and the gel polymer electrolyte. The separator includes a porous substrate and a ceramic coating layer disposed on both sides of the porous substrate, and the ceramic coating layer contains from 92 wt % to less than 100 wt % of inorganic particles and from greater than 0 wt % to 8 wt % of a binder.

Abstract: The present invention relates to a novel heterocyclic compound and a composition, for preventing or treating a cancer, an autoimmune disease, and an inflammatory disease, comprising same. The novel heterocyclic compound of the present invention is a bifunctional compound having a Bruton's tyrosine kinase (BTK) degradation function via a ubiquitin proteasome pathway, and may be utilized as a composition for preventing or treating a cancer, an autoimmune disease, and Parkinson's disease.

Abstract: The present disclosure relates to a secondary battery that includes an electrode assembly including an electrode and a separator which are alternately stacked, a gel polymer electrolyte, and a battery case accommodating the electrode assembly and the gel polymer electrolyte, wherein the separator includes a porous substrate and a ceramic coating layer disposed on both sides of the porous substrate, the ceramic coating layer includes inorganic particles in an amount of 92 wt % or greater and less than 100 wt % and a binder in an amount of greater than 0 wt % and 8 wt % or less, the electrode includes a positive electrode and a negative electrode, and the negative electrode includes a silicon-based active material.

Abstract: A method for manufacturing a secondary battery, includes preparing an electrode assembly in which electrodes and a separator are alternately laminated, and an adhesive composition is applied to the surface of at least one of the electrodes or the separator, thereby allowing the electrodes and the separator to adhere to each other; accommodating the electrode assembly in a battery case; injecting a gel polymer electrolyte composition into the battery case to impregnate the electrode assembly with the gel polymer electrolyte composition; curing the gel polymer electrolyte composition; and sealing the battery case, wherein the separator includes a porous substrate and ceramic coating layers disposed on both surfaces of the porous substrate.

Abstract: The present disclosure provides: a compound of a specific chemical structure, having excellent activity with respect to BTK degradation; or a pharmaceutically acceptable salt thereof. The present disclosure also provides a composition comprising the compound or pharmaceutically acceptable salts thereof. The present disclosure also provides are pharmaceutical use for treating or preventing BTK-associated diseases (for example, autoimmune diseases or cancer) of the compound, the salt thereof, and the composition comprising same according to the present disclosure. The present disclosure also provides a method for treating or preventing BTK-associated diseases (for example, autoimmune diseases or cancer), comprising administering, to a subject requiring treatment, an effective amount of the compound, the salt thereof, or the composition comprising same according to the present disclosure.

Abstract: A method for using a high bandwidth memory controller includes providing a clock signal having a first clock frequency, providing a write strobe signal having a second clock frequency, providing a write command/address signal based on the clock signal, and providing a write data signal based on the write strobe signal. The first clock frequency is half of the second clock frequency, the write strobe signal has two cycles of pre-amble before the write data signal, and the write strobe signal has two cycles of post-amble after the write data signal.

Abstract: A memory device includes a first channel including a first cell array and communicating with a memory controller through a first path, a second channel including a second cell array and communicating with the memory controller through a second path, and an assignment control circuit configured to monitor memory usage of the first and second channels and further assign a storage space of a portion of the second cell array to the first channel when the memory usage of the first cell array exceeds a threshold value. Access to the storage space of the portion of the second cell array assigned to the first channel is performed through the first path.

Abstract: A method for using a high bandwidth memory controller includes providing a clock signal having a first clock frequency, providing a write strobe signal having a second clock frequency, providing a write command/address signal based on the clock signal, and providing a write data signal based on the write strobe signal. The first clock frequency is half of the second clock frequency, the write strobe signal has two cycles of pre-amble before the write data signal, and the write strobe signal has two cycles of post-amble after the write data signal.

Abstract: A method for using a high bandwidth memory controller includes providing a clock signal having a first clock frequency, providing a write strobe signal having a second clock frequency, providing a write command/address signal based on the clock signal, and providing a write data signal based on the write strobe signal. The first clock frequency is half of the second clock frequency, the write strobe signal has two cycles of pre-amble before the write data signal, and the write strobe signal has two cycles of post-amble after the write data signal.

Abstract: A memory device includes a control logic circuit, a write data strobe signal divider, a data transceiver, and a memory cell array. The control logic circuit generates a reset signal before a write data strobe signal provided from a memory controller starts to toggle. The write data strobe signal divider generates internal write data strobe signals that toggle depending on toggling of the write data strobe signal, the internal write data strobe signals toggling with different phases, respectively. The control logic circuit initializes the internal write data strobe signals to given values in response to the reset signal. The data transceiver receives write data provided from the memory controller based on the internal write data strobe signals. The memory cell array stores the received write data.

Abstract: A semiconductor die may include a first delay circuit formed on a substrate and configured to delay a test signal, the first delay circuit including first delay stages connected in series, a second delay circuit formed on the substrate and configured to delay the test signal, the second delay circuit including second delay stages connected in series, at least one through silicon via connected to at least one output terminal of output terminals of the first delay stages, the at least one through silicon via penetrating through the substrate, and a load determinator configured to compare a first delay signal output from one of the first delay stages with a second delay signal output from one of the second delay stages and determine a load of the at least one through silicon via.

Abstract: A memory device includes a first channel including a first cell array and communicating with a memory controller through a first path, a second channel including a second cell array and communicating with the memory controller through a second path, and an assignment control circuit configured to monitor memory usage of the first and second channels and further assign a storage space of a portion of the second cell array to the first channel when the memory usage of the first cell array exceeds a threshold value. Access to the storage space of the portion of the second cell array assigned to the first channel is performed through the first path.

Abstract: A memory device includes a control logic circuit, a write data strobe signal divider, a data transceiver, and a memory cell array. The control logic circuit generates a reset signal before a write data strobe signal provided from a memory controller starts to toggle. The write data strobe signal divider generates internal write data strobe signals that toggle depending on toggling of the write data strobe signal, the internal write data strobe signals toggling with different phases, respectively. The control logic circuit initializes the internal write data strobe signals to given values in response to the reset signal. The data transceiver receives write data provided from the memory controller based on the internal write data strobe signals. The memory cell array stores the received write data.

Abstract: A memory device includes a first channel including a first cell array and communicating with a memory controller through a first path, a second channel including a second cell array and communicating with the memory controller through a second path, and an assignment control circuit configured to monitor memory usage of the first and second channels and further assign a storage space of a portion of the second cell array to the first channel when the memory usage of the first cell array exceeds a threshold value. Access to the storage space of the portion of the second cell array assigned to the first channel is performed through the first path.

Abstract: A semiconductor die may include a first delay circuit formed on a substrate and configured to delay a test signal, the first delay circuit including first delay stages connected in series, a second delay circuit formed on the substrate and configured to delay the test signal, the second delay circuit including second delay stages connected in series, at least one through silicon via connected to at least one output terminal of output terminals of the first delay stages, the at least one through silicon via penetrating through the substrate, and a load determinator configured to compare a first delay signal output from one of the first delay stages with a second delay signal output from one of the second delay stages and determine a load of the at least one through silicon via.

Abstract: A semiconductor die may include a first delay circuit formed on a substrate and configured to delay a test signal, the first delay circuit including first delay stages connected in series, a second delay circuit formed on the substrate and configured to delay the test signal, the second delay circuit including second delay stages connected in series, at least one through silicon via connected to at least one output terminal of output terminals of the first delay stages, the at least one through silicon via penetrating through the substrate, and a load determinator configured to compare a first delay signal output from one of the first delay stages with a second delay signal output from one of the second delay stages and determine a load of the at least one through silicon via.

Abstract: A stacked memory includes a logic semiconductor die, a plurality of memory semiconductor dies stacked with the logic semiconductor die, a plurality of through-silicon vias (TSVs) electrically connecting the logic semiconductor die and the memory semiconductor dies, a global processor disposed in the logic semiconductor die and configured to perform a global sub process corresponding to a portion of a data process, a plurality of local processors respectively disposed in the memory semiconductor dies and configured to perform local sub processes corresponding to other portions of the data process and a plurality of memory integrated circuits respectively disposed in the memory semiconductor dies and configured to store data associated with the data process.