Patents by Inventor Je-Min Wen

Je-Min Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230187144
    Abstract: A capacitor structure includes a first comb-shaped electrode, a second comb-shaped electrode, a bottom electrode, an insulator layer, and a top electrode. The first comb-shaped electrode has a first pad and first fingers connecting to the first pad. The second comb-shaped electrode has a second pad and second fingers connecting to the first pad, wherein one of the second fingers is disposed between two adjacent first fingers. The bottom electrode includes a first portion, a second portion and a third portion which are spaced apart, wherein the first portion and the third portion are electrically coupled to the first comb-shaped electrode and the second comb-shaped electrode, respectively. The insulator layer is disposed over the bottom electrode. The top electrode is disposed over the insulator layer.
    Type: Application
    Filed: November 14, 2022
    Publication date: June 15, 2023
    Inventors: Je-Min WEN, Cheng-Hua LIN, Ching-Han JAN
  • Publication number: 20200027985
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first silicon layer, an insulating layer on the first silicon layer, and a second silicon layer on the insulating layer; forming a metal-oxide semiconductor (MOS) transistor on the substrate; forming an interlayer dielectric layer (ILD) on the MOS transistor; removing part of the ILD layer to form a first trench to expose the insulating layer; and performing a wet etching process through the first trench to remove part of the insulating layer for forming a first air gap under the MOS transistor.
    Type: Application
    Filed: August 22, 2018
    Publication date: January 23, 2020
    Inventors: Purakh Raj Verma, Chih-Wei Su, Je-Min Wen
  • Patent number: 10529854
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first silicon layer, an insulating layer on the first silicon layer, and a second silicon layer on the insulating layer; forming a metal-oxide semiconductor (MOS) transistor on the substrate; forming an interlayer dielectric layer (ILD) on the MOS transistor; removing part of the ILD layer to form a first trench to expose the insulating layer; and performing a wet etching process through the first trench to remove part of the insulating layer for forming a first air gap under the MOS transistor.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: January 7, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Chih-Wei Su, Je-Min Wen