Patents by Inventor Jea-won Kim

Jea-won Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11968915
    Abstract: A selector according to an embodiment of the present disclosure includes a first electrode; a second electrode disposed opposite to the first electrode; an ion supply layer disposed between the first electrode and the second electrode to be on the side of the first electrode and doped with a metal, wherein the doped metal diffuses toward the second electrode; a switching layer disposed between the first electrode and the second electrode to be on the side of the second electrode, wherein the doped metal diffuses from the ion supply layer into the switching layer so that metal concentration distribution inside the switching layer is changed to generate metal filaments; and a diffusion control layer inserted between the ion supply layer and the switching layer, wherein the diffusion control layer serves to adjust electrical characteristics related to the generated metal filaments as the amount of the diffusing metal is adjusted in proportion to a thickness of the diffusion control layer.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: April 23, 2024
    Assignee: IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)
    Inventors: Jea Gun Park, Soo Min Jin, Dong Won Kim, Hea Jee Kim, Dae Seong Woo, Sang Hong Park, Sung Mok Jung, Dong Eon Kim
  • Patent number: 11876012
    Abstract: A method of manufacturing a semiconductor package substrate includes forming a trench and a post by etching an upper surface of a base substrate including a conductive material, filling the trench with a resin, removing the resin exposed to outside of the trench such that an upper surface of the post and an upper surface of the resin are at same level, forming a conductive layer on an entire area of the upper surface of the post and the upper surface of the resin, and forming a circuit wiring including an upper circuit wiring and a lower circuit wiring by simultaneously patterning the conductive layer and a lower surface of the base substrate.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: January 16, 2024
    Assignee: HAESUNG DS CO., LTD.
    Inventors: Sung Il Kang, In Seob Bae, Jea Won Kim
  • Publication number: 20230130743
    Abstract: Proposed is an artificial ankle joint bearing element in which a contact area of the bearing element with a talus element is increased such that stress is evenly distributed during bearing movement of the bearing element on the talus element and wear of the bearing element is reduced under the same load; the bearing element has a front and a rear convexly formed to increase a contact area with a tibial element and distribute stress; and the front and rear of the bearing element are asymmetrically formed such that the rear thereof is formed to have a smaller height than the front thereof so as to facilitate the insertion of the bearing element into space between the talus element and the tibial element from an anterior side thereof during artificial ankle joint surgery.
    Type: Application
    Filed: March 9, 2021
    Publication date: April 27, 2023
    Inventors: Keun-Bae Lee, Jea-Won Kim, Sung-Wook Jung
  • Patent number: 11139220
    Abstract: A flexible semiconductor package includes a semiconductor chip accommodated in a cavity formed in a substrate, a molding layer covering an entire upper surface of the substrate and the cavity, and a wiring portion including an insulating layer and a redistribution member provided under lower surfaces of the substrate and the semiconductor chip, wherein the molding layer includes a pre-preg in which a resin is impregnated with a glass fabric, and the molding layer and the insulating layer are attached to the semiconductor chip accommodated in the cavity by a roll-to-roll continuous process.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: October 5, 2021
    Assignee: HAESUNG DS CO., LTD.
    Inventors: Jea Won Kim, Chong Han Park, Jong Woo Park
  • Publication number: 20210057301
    Abstract: A flexible semiconductor package includes a semiconductor chip accommodated in a cavity formed in a substrate, a molding layer covering an entire upper surface of the substrate and the cavity, and a wiring portion including an insulating layer and a redistribution member provided under lower surfaces of the substrate and the semiconductor chip, wherein the molding layer includes a pre-preg in which a resin is impregnated with a glass fabric, and the molding layer and the insulating layer are attached to the semiconductor chip accommodated in the cavity by a roll-to-roll continuous process.
    Type: Application
    Filed: April 21, 2020
    Publication date: February 25, 2021
    Inventors: Jea Won KIM, Chong Han PARK, Jong Woo PARK
  • Publication number: 20200411362
    Abstract: A method of manufacturing a semiconductor package substrate includes forming a trench and a post by etching an upper surface of a base substrate including a conductive material, filling the trench with a resin, removing the resin exposed to outside of the trench such that an upper surface of the post and an upper surface of the resin are at same level, forming a conductive layer on an entire area of the upper surface of the post and the upper surface of the resin, and forming a circuit wiring including an upper circuit wiring and a lower circuit wiring by simultaneously patterning the conductive layer and a lower surface of the base substrate.
    Type: Application
    Filed: September 11, 2020
    Publication date: December 31, 2020
    Inventors: Sung Il KANG, In Seob BAE, Jea Won KIM
  • Patent number: 10811302
    Abstract: A method of manufacturing a semiconductor package substrate includes forming a trench and a post by etching an upper surface of a base substrate including a conductive material, filling the trench with a resin, removing the resin exposed to outside of the trench such that an upper surface of the post and an upper surface of the resin are at same level, forming a conductive layer on an entire area of the upper surface of the post and the upper surface of the resin, and forming a circuit wiring including an upper circuit wiring and a lower circuit wiring by simultaneously patterning the conductive layer and a lower surface of the base substrate.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: October 20, 2020
    Assignee: HAESUNG DS CO., LTD.
    Inventors: Sung II Kang, In Seob Bae, Jea Won Kim
  • Publication number: 20190067082
    Abstract: A method of manufacturing a semiconductor package substrate includes forming a trench and a post by etching an upper surface of a base substrate including a conductive material, filling the trench with a resin, removing the resin exposed to outside of the trench such that an upper surface of the post and an upper surface of the resin are at same level, forming a conductive layer on an entire area of the upper surface of the post and the upper surface of the resin, and forming a circuit wiring including an upper circuit wiring and a lower circuit wiring by simultaneously patterning the conductive layer and a lower surface of the base substrate.
    Type: Application
    Filed: August 30, 2018
    Publication date: February 28, 2019
    Inventors: Sung Il KANG, In Seob BAE, Jea Won KIM
  • Publication number: 20070081743
    Abstract: An image interpolation apparatus includes: a frequency component detecting part detecting a frequency component in the unit of pixel data included in an input image signal; a coefficient storing part storing a plurality of interpolation coefficients corresponding to a plurality of frequency component sections; a coefficient controlling part selecting a certain interpolation coefficient corresponding to the frequency component detected in the unit of pixel data at the coefficient storing part; and an interpolation filtering part filtering the pixel data with the selected interpolation coefficient and outputting the interpolated pixel data. Accordingly, an interpolation adaptive to images in high and low frequency areas are performed to output enhanced picture quality.
    Type: Application
    Filed: March 31, 2006
    Publication date: April 12, 2007
    Inventor: Jea-won Kim
  • Publication number: 20050270427
    Abstract: A method of adaptively controlling saturation of an input image according to characteristics of the input image includes a saturation calculating unit to sequentially calculate saturation values of each pixel composing an input image, and to output the calculated saturation values, a histogram analysis unit to accumulate interval values, each interval value corresponding to the saturation value of pixel and being allocated to at least one of two intervals, to calculate a gain corresponding to a cumulative value of each interval, and to output the gain, and a total gain calculating unit to calculate a total gain from the transferred gains of the respective intervals.
    Type: Application
    Filed: June 1, 2005
    Publication date: December 8, 2005
    Inventors: Jea-won Kim, Jin-Sub Um, Moon-cheol Kim