Abstract: An imaging pixel formed by a photodetector connected to a reading circuit comprising: an integration capacitance, a transistor for resetting the integration capacitance, a coupling transistor between the photodetector and the integration capacitance, a memorisation capacitance, a second transistor for resetting the memorisation capacitance, a memorisation switch between the integration capacitance and the memorisation capacitance, to enable different configurations corresponding to different phases of assessing parameters of the pixel and in particular a ratio R=Cint/Cmem.

Abstract: Imager readout circuit comprising: an active reset stage of the integration capacitor equipped with a first current amplifier, a buffered direct injection bias stage of the photodetector equipped with transistors forming a second current amplifier, a switching circuit comprising a coupling stage integrated in the readout circuit, the switching circuit being controlled by control signals and being configured to: during a reset phase of the integration capacitor corresponding to a first state of said control signals: couple said first current source to the integration capacitor and activate the first current amplifier while uncoupling said second current source of the photodetector and deactivating the second amplifier, during an integration phase of a current from the photodiode and corresponding to a second state of said control signals, couple said second current source to the photodetector and activate the second current amplifier while uncoupling said first current source of the integration capacitor an

Abstract: External biasing control unit for a reading circuit of an infrared photodetector element, the control unit being able to adopt: a first configuration wherein it sends a first set of biasing signals to a first stage of the reading circuit so that this first stage adopts a first operating mode corresponding to a first biasing mode of the photodetector, in particular a direct injection mode, a second configuration wherein it sends a second set of biasing signals to said first stage, the signals in the second set being designed so that said first stage adopts a second operating mode corresponding to a second biasing mode of the photodetector, in particular a buffer direct injection mode.

Abstract: External biasing control unit for a reading circuit of an infrared photodetector element, the control unit being able to adopt: a first configuration wherein it sends a first set of biasing signals to a first stage of the reading circuit so that this first stage adopts a first operating mode corresponding to a first biasing mode of the photodetector, in particular a direct injection mode, a second configuration wherein it sends a second set of biasing signals to said first stage, the signals in the second set being designed so that said first stage adopts a second operating mode corresponding to a second biasing mode of the photodetector, in particular a buffer direct injection mode.

Abstract: A summing circuit, including a capacitor, a switching circuit capable of connecting the capacitor between a first node (ana) and a second node (ref), between a third node and the second node in a first connection direction or between the third node and the second node in a second connection direction, an integrator coupled to the third node, a hysteresis comparator coupled to the output of the integrator, and a counter coupled to the output of the hysteresis comparator.

Abstract: A summing circuit, including a capacitor, a switching circuit capable of connecting the capacitor between a first node (ana) and a second node (ref), between a third node and the second node in a first connection direction or between the third node and the second node in a second connection direction, an integrator coupled to the third node, a hysteresis comparator coupled to the output of the integrator, and a counter coupled to the output of the hysteresis comparator.

Abstract: The invention relates to an integrated circuit comprising a succession of N identical elementary circuits (CE1, CE2, . . . CEN), juxtaposed in the order of their rank j varying from 1 to N, N being at least equal to 50, and all having to receive two reference potentials Vref and V0 supplied by two conductors. An upstream input of the second conductor is situated geographically on the side of the rank 1 of the succession of juxtaposed circuits, and an upstream input of the first conductor is situated geographically on the side of the rank N of the succession of juxtaposed circuits. This reduces the error in the potential difference applied to the elementary circuits all along the succession, an error that originates from the non-zero resistance of the conductors. The integrated circuit is applicable to analog-digital converters or digital-analog converters with high resolution.

Abstract: The invention relates to fast, high resolution, analog digital converters, and more particularly those which possess at least one conversion stage of “flash” type. The converter according to the invention uses N differential amplifiers with four inputs. The amplifier of rank j receives the input voltage to be converted Vep?Ven on two first inputs, and a reference potential difference on two other inputs. The reference potential difference is obtained between two taps of networks of resistors that are identical operating in parallel and supplied between a high voltage source and a low current source; the taps for an amplifier are respectively a tap Pj of rank j of a first network and a tap P?N?j+1 of rank N?j+1 of a second network. This reduces the first and second order non-linearity effects due to the fact that the differential amplifiers consume an input current tapped off from the networks of resistors.

Abstract: The invention relates to an integrated circuit comprising a succession of N identical elementary circuits, juxtaposed in the order of their rank j varying from 1 to N, N being at least equal to 50, and all having to receive two reference potentials Vref and V0 supplied by two conductors. The upstream input of the second conductor is situated geographically on the side of the rank 1 of the succession of juxtaposed circuits, and the upstream input of the first conductor is situated geographically on the side of the rank N of the succession of juxtaposed circuits. This reduces the error in the potential difference applied to the elementary circuits all along the succession, an error that originates from the non-zero resistance of the conductors. Application to analog-digital converters or digital-analog converters with high resolution (10 bits or more).

Abstract: The invention relates to fast, high resolution, analog digital converters, and more particularly those which possess at least one conversion stage of “flash” type. The converter according to the invention uses N differential amplifiers with four inputs. The amplifier of rank j receives the input voltage to be converted Vep?Ven on two first inputs, and a reference potential difference on two other inputs. The reference potential difference is obtained between two taps of networks of resistors that are identical operating in parallel and supplied between a high voltage source and a low current source; the taps for an amplifier are respectively a tap Pj of rank j of a first network and a tap P?N?j+1 of rank N?j+1 of a second network. This reduces the first and second order non-linearity effects due to the fact that the differential amplifiers consume an input current tapped off from the networks of resistors.