Patents by Inventor Jean Audet
Jean Audet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10224273Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and a interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.Type: GrantFiled: October 28, 2017Date of Patent: March 5, 2019Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Jean Audet, Brian W. Quinlan, Charles L. Reynolds, Brian R. Sundlof
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Patent number: 10224274Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and a interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.Type: GrantFiled: October 28, 2017Date of Patent: March 5, 2019Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Jean Audet, Brian W. Quinlan, Charles L. Reynolds, Brian R. Sundlof
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Patent number: 10211174Abstract: A flip chip assembly is disclosed that includes a die with die circuitry and a plurality of electrical contacts electrically connected to the die circuitry. A substrate includes electrical contacts that are juxtaposed with and electrically connected to corresponding die electrical contacts. A passive component is disposed between the die and the substrate, and includes a dielectric disposed between a first electrode and a second electrode. The first electrode is electrically connected to a first of the die electrical contacts and a corresponding substrate electrical contact, and the second electrode is electrically connected to a second of the die electrical contacts and a corresponding substrate electrical contact.Type: GrantFiled: January 3, 2017Date of Patent: February 19, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jean Audet, Luc G. Guerin, Richard Langlois, Stephan L. Martel, Sylvain E. Ouimet
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Patent number: 9984988Abstract: A flip chip assembly is disclosed that includes a die with die circuitry and a plurality of electrical contacts electrically connected to the die circuitry. A substrate includes electrical contacts that are juxtaposed with and electrically connected to corresponding die electrical contacts. A passive component is disposed between the die and the substrate, and includes a dielectric disposed between a first electrode and a second electrode. The first electrode is electrically connected to a first of the die electrical contacts and a corresponding substrate electrical contact, and the second electrode is electrically connected to a second of the die electrical contacts and a corresponding substrate electrical contact.Type: GrantFiled: January 3, 2017Date of Patent: May 29, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jean Audet, Luc G. Guerin, Richard Langlois, Stephan L. Martel, Sylvain E. Ouimet
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Publication number: 20180068945Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and a interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.Type: ApplicationFiled: October 28, 2017Publication date: March 8, 2018Inventors: Charles L. Arvin, Jean Audet, Brian W. Quinlan, Charles L. Reynolds, Brian R. Sundlof
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Publication number: 20180053717Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and a interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.Type: ApplicationFiled: October 28, 2017Publication date: February 22, 2018Inventors: Charles L. Arvin, Jean Audet, Brian W. Quinlan, Charles L. Reynolds, Brian R. Sundlof
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Patent number: 9899313Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and an interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.Type: GrantFiled: July 11, 2016Date of Patent: February 20, 2018Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Jean Audet, Brian W. Quinlan, Charles L. Reynolds, Brian R. Sundlof
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Publication number: 20180012838Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc. includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and an interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.Type: ApplicationFiled: July 11, 2016Publication date: January 11, 2018Inventors: Charles L. Arvin, Jean Audet, Brian W. Quinlan, Charles L. Reynolds, Brian R. Sundlof
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Publication number: 20170170134Abstract: A flip chip assembly is disclosed that includes a die with die circuitry and a plurality of electrical contacts electrically connected to the die circuitry. A substrate includes electrical contacts that are juxtaposed with and electrically connected to corresponding die electrical contacts. A passive component is disposed between the die and the substrate, and includes a dielectric disposed between a first electrode and a second electrode. The first electrode is electrically connected to a first of the die electrical contacts and a corresponding substrate electrical contact, and the second electrode is electrically connected to a second of the die electrical contacts and a corresponding substrate electrical contact.Type: ApplicationFiled: January 3, 2017Publication date: June 15, 2017Inventors: JEAN AUDET, LUC G. GUERIN, RICHARD LANGLOIS, STEPHAN L. MARTEL, SYLVAIN E. OUIMET
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Publication number: 20170170133Abstract: A flip chip assembly is disclosed that includes a die with die circuitry and a plurality of electrical contacts electrically connected to the die circuitry. A substrate includes electrical contacts that are juxtaposed with and electrically connected to corresponding die electrical contacts. A passive component is disposed between the die and the substrate, and includes a dielectric disposed between a first electrode and a second electrode. The first electrode is electrically connected to a first of the die electrical contacts and a corresponding substrate electrical contact, and the second electrode is electrically connected to a second of the die electrical contacts and a corresponding substrate electrical contact.Type: ApplicationFiled: January 3, 2017Publication date: June 15, 2017Inventors: JEAN AUDET, LUC G. GUERIN, RICHARD LANGLOIS, STEPHAN L. MARTEL, SYLVAIN E. OUIMET
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Patent number: 9673064Abstract: A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for dielectric fields. Each unit cell is then filled with a dielectric material. Thereafter, holes (i.e., through holes or blind holes) are created within the dielectric material in the cells. After hole formation, a conductive metal is formed into each of the holes providing an interposer. This method can enable fine pitch processing in organic-based materials, isolates the thermal coefficient of expansion (TCE) stress from metal vias to low TCE carriers and creates a path to high volume, low costs components in panel form.Type: GrantFiled: October 3, 2015Date of Patent: June 6, 2017Assignee: International Business Machines CorporationInventors: Jean Audet, Benjamin V. Fasano, Shidong Li
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Patent number: 9553079Abstract: A flip chip assembly is disclosed that includes a die with die circuitry and a plurality of electrical contacts electrically connected to the die circuitry. A substrate includes electrical contacts that are juxtaposed with and electrically connected to corresponding die electrical contacts. A passive component is disposed between the die and the substrate, and includes a dielectric disposed between a first electrode and a second electrode. The first electrode is electrically connected to a first of the die electrical contacts and a corresponding substrate electrical contact, and the second electrode is electrically connected to a second of the die electrical contacts and a corresponding substrate electrical contact.Type: GrantFiled: December 15, 2015Date of Patent: January 24, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jean Audet, Luc G. Guerin, Richard Langlois, Stephan L. Martel, Sylvain E. Ouimet
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Publication number: 20160372337Abstract: A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for dielectric fields. Each unit cell is then filled with a dielectric material. Thereafter, holes (i.e., through holes or blind holes) are created within the dielectric material in the cells. After hole formation, a conductive metal is formed into each of the holes providing an interposer. This method can enable fine pitch processing in organic-based materials, isolates the thermal coefficient of expansion (TCE) stress from metal vias to low TCE carriers and creates a path to high volume, low costs components in panel form.Type: ApplicationFiled: September 2, 2016Publication date: December 22, 2016Inventors: Jean Audet, Benjamin V. Fasano, Shidong Li
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Patent number: 9443799Abstract: A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for dielectric fields. Each unit cell is then filled with a dielectric material. Thereafter, holes (i.e., through holes or blind holes) are created within the dielectric material in the cells. After hole formation, a conductive metal is formed into each of the holes providing an interposer. This method can enable fine pitch processing in organic-based materials, isolates the thermal coefficient of expansion (TCE) stress from metal vias to low TCE carriers and creates a path to high volume, low costs components in panel form.Type: GrantFiled: December 16, 2014Date of Patent: September 13, 2016Assignee: International Business Machines CorporationInventors: Jean Audet, Benjamin V. Fasano, Shidong Li
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Publication number: 20160211229Abstract: A multi-layer substrate with metal layers as a moisture diffusion barrier for reduced electrical performance degradation over time after moisture exposure and methods of design and manufacture. The method includes determining a diffusion rate of an insulator material provided between an upper metal layer and an underlying signal line. The method further includes calculating a diffusion distance between a plane opening of the upper metal layer and the underlying signal line using the diffusion rate of the insulator material.Type: ApplicationFiled: March 14, 2016Publication date: July 21, 2016Applicant: Kyocera Circuit Solutions Inc.Inventors: Jean AUDET, Edmund D. BLACKSHEAR, Masahiro FUKUI, Charles L. REYNOLDS, Kenji TERADA, Tomoyuki YAMADA
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Publication number: 20160211481Abstract: A multi-layer substrate with metal layers as a moisture diffusion barrier for reduced electrical performance degradation over time after moisture exposure and methods of design and manufacture. The method includes determining a diffusion rate of an insulator material provided between an upper metal layer and an underlying signal line. The method further includes calculating a diffusion distance between a plane opening of the upper metal layer and the underlying signal line using the diffusion rate of the insulator material.Type: ApplicationFiled: January 15, 2015Publication date: July 21, 2016Applicant: KYOCERA CIRCUIT SOLUTIONS INC.Inventors: Jean AUDET, Edmund D. BLACKSHEAR, Masahiro FUKUI, Charles L. REYNOLDS, Kenji TERADA, Tomoyuki YAMADA
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Publication number: 20160210398Abstract: A multi-layer substrate with metal layers as a moisture diffusion barrier for reduced electrical performance degradation over time after moisture exposure and methods of design and manufacture. The method includes determining a diffusion rate of an insulator material provided between an upper metal layer and an underlying signal line. The method further includes calculating a diffusion distance between a plane opening of the upper metal layer and the underlying signal line using the diffusion rate of the insulator material.Type: ApplicationFiled: March 14, 2016Publication date: July 21, 2016Applicant: Kyocera Circuit Solutions Inc.Inventors: Jean AUDET, Edmund D. BLACKSHEAR, Masahiro FUKUI, Charles L. REYNOLDS, Kenji TERADA, Tomoyuki YAMADA
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Publication number: 20160172290Abstract: A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for dielectric fields. Each unit cell is then filled with a dielectric material. Thereafter, holes (i.e., through holes or blind holes) are created within the dielectric material in the cells. After hole formation, a conductive metal is formed into each of the holes providing an interposer. This method can enable fine pitch processing in organic-based materials, isolates the thermal coefficient of expansion (TCE) stress from metal vias to low TCE carriers and creates a path to high volume, low costs components in panel form.Type: ApplicationFiled: October 3, 2015Publication date: June 16, 2016Inventors: Jean Audet, Benjamin V. Fasano, Shidong Li
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Publication number: 20160172288Abstract: A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for dielectric fields. Each unit cell is then filled with a dielectric material. Thereafter, holes (i.e., through holes or blind holes) are created within the dielectric material in the cells. After hole formation, a conductive metal is formed into each of the holes providing an interposer. This method can enable fine pitch processing in organic-based materials, isolates the thermal coefficient of expansion (TCE) stress from metal vias to low TCE carriers and creates a path to high volume, low costs components in panel form.Type: ApplicationFiled: December 16, 2014Publication date: June 16, 2016Inventors: Jean Audet, Benjamin V. Fasano, Shidong Li
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Patent number: 8841209Abstract: A method for forming coreless flip chip ball grid array (FCBGA) substrates comprising the steps of sequentially depositing a pair of laminates, each having a plurality of insulated metallization layers simultaneously respectively on each side of a temporary carrier substrate, and then removing the temporary carrier to separate the pair of laminates, so that each laminate has an outer ball grid metal pad array, and during the depositing of the pair of laminates on the carrier substrate, further depositing a supporting layer of dielectric material enclosing the metal pad array, wherein said supporting layers of dielectric material provides structural support for each of the laminates after the separation.Type: GrantFiled: August 18, 2011Date of Patent: September 23, 2014Assignee: International Business Machines CorporationInventors: Sylvie Allard, Jean Audet, Kevin Arthur Dore, Sylvain Pharand, David John Russell