Abstract: A temperature correction circuit and method for maintaining a transistor of a power amplifier in a linear operating region of the transistor. The temperature correction circuit includes a first current source circuit operable to provide a first correction current proportional to an absolute temperature of a semiconductor die including the transistor. The temperature correction circuit also includes a second current source circuit operable to provide a second correction current proportional to a change in temperature of a part of the semiconductor die in which the transistor is located during operation of the transistor. The temperature correction circuit further includes a third current source circuit operable to provide a gain selection current. The temperature correction circuit also includes circuitry for producing a reference current from the first and second correction currents and the gain current.

Abstract: A temperature correction circuit and method for maintaining a transistor of a power amplifier in a linear operating region of the transistor. The temperature correction circuit includes a first current source circuit operable to provide a first correction current proportional to an absolute temperature of a semiconductor die including the transistor. The temperature correction circuit also includes a second current source circuit operable to provide a second correction current proportional to a change in temperature of a part of the semiconductor die in which the transistor is located during operation of the transistor. The temperature correction circuit further includes a third current source circuit operable to provide a gain selection current. The temperature correction circuit also includes circuitry for producing a reference current from the first and second correction currents and the gain current.

Abstract: Continuous time analog/digital converter, comprising a sigma delta modulator (MSD1) configured to receive an analog input signal (x(t)) and comprising high-pass filtering means (MF) the chopping frequency of which is equal to half of the sampling frequency (Fs) of the quantization means (QTZ) of the modulator (MSD1).

Abstract: A fractional frequency divider including a frequency division unit for generating a reduced frequency timing signal having j pulses for every k pulses of an original timing signal, wherein j and k are each integers; and phase correction circuitry adapted to selectively shift each jth pulse of the reduced frequency timing signal by a first fixed time period.

Abstract: Continuous time analogue/digital converter, comprising a sigma delta modulator (MSD1) configured to receive an analogue input signal (x(t)) and comprising high-pass filtering means (MF) the chopping frequency of which is equal to half of the sampling frequency (Fs) of the quantization means (QTZ) of the modulator (MSD1).

Abstract: Device for generating a signal of parametrizable frequency comprising a phase locked loop including a generator of a reference signal, a phase-frequency comparator comprising a first input for receiving the reference signal, an oscillator controlled on the basis of the result output by the phase-frequency comparator, a fractional divider coupled between an output of the oscillator and a second input of the phase-frequency comparator, and a selector selectively linking an input of the oscillator either with an input of the generator, or with the output of the oscillator as a function of the multiplication ratio of the fractional divider.

Abstract: Continuous time analogue/digital converter, comprising a sigma delta modulator (MSD1) configured to receive an analogue input signal (x(t)) and comprising high-pass filtering means (MF) the chopping frequency of which is equal to half of the sampling frequency (Fs) of the quantization means (QTZ) of the modulator (MSD1).

Abstract: A device for extracting a clock signal from a baseband serial signal, includes an injection-locked oscillator (19), a phase-locked loop (25) including a digital phase detector (26). The oscillator (19) includes a digital input for controlling the value of its natural frequency, and the phase-locked loop (25) includes a counting circuit (30, 35) aggregating the relative values of the digital signal supplied by the digital phase detector (26) and supplying a control signal in digital form for the oscillator (19).

Abstract: Device for generating a signal of parametrizable frequency comprising a phase locked loop including a generator of a reference signal, a phase-frequency comparator comprising a first input for receiving the reference signal, an oscillator controlled on the basis of the result output by the phase-frequency comparator, a fractional divider coupled between an output of the oscillator and a second input of the phase-frequency comparator, and a selector selectively linking an input of the oscillator either with an input of the generator, or with the output of the oscillator as a function of the multiplication ratio of the fractional divider.

Abstract: A fractional frequency divider including a frequency division unit for generating a reduced frequency timing signal having j pulses for every k pulses of an original timing signal, wherein j and k are each integers; and phase correction circuitry adapted to selectively shift each jth pulse of the reduced frequency timing signal by a first fixed time period.

Abstract: A device processes a received radio signal. Circuitry formulates voltage samples of the radio signal. Analog processing of those samples is performed. Then, digital processing is performed on the output of the analog processing. The circuitry for formulating voltage samples is configured to ensure a processing of the samples prior to the digital processing.

Abstract: Continuous time analogue/digital converter, comprising a sigma delta modulator (MSD1) configured to receive an analogue input signal (x(t)) and comprising high-pass filtering means (MF) the chopping frequency of which is equal to half of the sampling frequency (Fs) of the quantization means (QTZ) of the modulator (MSD1).

Abstract: A millimeter wave transformer including, at its primary, a turn formed of a conductive track made in at least one first metallization level, and, at its secondary, a winding in front of the primary turn, including at least one turn formed of a conductive track made in at least one second metallization level isolated from the at least one first level, the track width of the primary turn being at least equal to the total width of the secondary winding.

Abstract: A method is for reducing a DC component of an input signal transposed into baseband and being generated by a first frequency transposition stage starting from an initial signal and from a transposition signal. The method includes amplifying the transposed input signal in a first amplifier. The first amplifier receives at a DC offset compensation input, a compensation signal extracted from an output signal of a second amplifier subjected to a compensation of a offset DC voltage of the second amplifier. The method also included alternating between receiving at an input of the second amplifier, a first auxiliary signal from an auto-transposition of a transposition signal in a second frequency transposition stage and a second auxiliary signal from a transposition of the initial signal in the second frequency transposition stage with the transposition signal.

Abstract: A device for extracting a clock signal from a baseband serial signal, includes an injection-locked oscillator (19), a phase-locked loop (25) including a digital phase detector (26). The oscillator (19) includes a digital input for controlling the value of its natural frequency, and the phase-locked loop (25) includes a counting circuit (30, 35) aggregating the relative values of the digital signal supplied by the digital phase detector (26) and supplying a control signal in digital form for the oscillator (19).

Abstract: A distributed oscillator includes an odd number of serially connected amplifying elements. An output of a last amplifying element is looped back to an input of a first amplifying element via a first transmission line. The oscillator oscillates at a first frequency f1. The oscillator further includes circuitry for injecting a control signal onto the input of the first amplifying element. The control signal has a second frequency f2 which is a sub-multiple of the first frequency f1.

Abstract: A device processes a received radio signal. Circuitry formulates voltage samples of the radio signal. Analog processing of those samples is performed. Then, digital processing is performed on the output of the analog processing. The circuitry for formulating voltage samples is configured to ensure a processing of the samples prior to the digital processing.

Abstract: A method is for reducing a DC component of an input signal transposed into baseband and being generated by a first frequency transposition stage starting from an initial signal and from a transposition signal. The method includes amplifying the transposed input signal in a first amplifier. The first amplifier receives at a DC offset compensation input, a compensation signal extracted from an output signal of a second amplifier subjected to a compensation of a offset DC voltage of the second amplifier. The method also included alternating between receiving at an input of the second amplifier, a first auxiliary signal from an auto-transposition of a transposition signal in a second frequency transposition stage and a second auxiliary signal from a transposition of the initial signal in the second frequency transposition stage with the transposition signal.

Abstract: A phase locked loop includes a controlled oscillator for delivering an output signal at a determined output frequency, and a variable frequency divider for converting the output signal into a signal at divided frequency. The PLL is termed composite in that it includes at least one first loop having a loop filter for generating a first control signal for the oscillator on the basis of the signal at divided frequency, and a second loop having a loop filter, different from the loop filter of the first loop, for generating, on the basis of the signal at divided frequency, a second signal for additional control of the oscillator. The loop filter of the first loop and the loop filter of the second loop have different respective cutoff frequencies. The passband of the first loop, can be adapted to ensure the convergence and the stability of the PLL, while the second loop can afford extra passband increasing the speed of adaptation of the PLL in case of modification of the value of a preset for the output frequency.

Abstract: A phase locked loop includes a controlled oscillator for delivering an output signal at a determined output frequency, and a variable frequency divider for converting the output signal into a signal at divided frequency. The PLL is termed composite in that it includes at least one first loop having a loop filter for generating a first control signal for the oscillator on the basis of the signal at divided frequency, and a second loop having a loop filter, different from the loop filter of the first loop, for generating, on the basis of the signal at divided frequency, a second signal for additional control of the oscillator. The loop filter of the first loop and the loop filter of the second loop have different respective cutoff frequencies. The passband of the first loop, can be adapted to ensure the convergence and the stability of the PLL, while the second loop can afford extra passband increasing the speed of adaptation of the PLL in case of modification of the value of a preset for the output frequency.