Patents by Inventor Jean-Baptiste Laloe

Jean-Baptiste Laloe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for forming a metal gate including de-oxidation of an oxidized surface of the metal gate utilizing a reducing agent
    Patent number: 10854472
    Abstract: Aspects of the present invention relate to approaches for forming a semiconductor device such as a field-effect-transistor (FET) having a metal gate with improved performance. A metal gate is formed on a substrate in the semiconductor device. Further processing can result in unwanted oxidation in the metal that forms the metal gate. A reducing agent can be used to de-oxidize the metal that forms the metal gate, leaving a substantially non-oxidized surface.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: December 1, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Huang Liu, Wen-Pin Peng, Jean-Baptiste Laloe
  • Depositing an etch stop layer before a dummy cap layer to improve gate performance
    Patent number: 9209258
    Abstract: An improved method for fabricating a semiconductor device is provided. The method includes: depositing a dielectric layer on a substrate; depositing a first cap layer on the dielectric layer; depositing an etch stop layer on the dielectric layer; and depositing a dummy cap layer on the etch stop layer to form a partial gate structure. Also provided is a partially formed semiconductor device. The partially formed semiconductor device includes: a substrate; a dielectric layer on the substrate; a first cap layer on the dielectric layer; an etch stop layer on the dielectric layer; and a dummy cap layer on the etch stop layer forming a partial gate structure.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: December 8, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Feng Zhou, Tien-Ying Luo, Haiting Wang, Padmaja Nagaiah, Jean-Baptiste Laloe, Isabelle Pauline Ferain, Yong Meng Lee
  • DE-OXIDATION OF METAL GATE FOR IMPROVED GATE PERFORMANCE
    Publication number: 20150270142
    Abstract: Aspects of the present invention relate to approaches for forming a semiconductor device such as a field-effect-transistor (FET) having a metal gate with improved performance. A metal gate is formed on a substrate in the semiconductor device. Further processing can result in unwanted oxidation in the metal that forms the metal gate. A reducing agent can be used to de-oxidize the metal that forms the metal gate, leaving a substantially non-oxidized surface.
    Type: Application
    Filed: March 19, 2014
    Publication date: September 24, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Huang Liu, Wen-Pin Peng, Jean-Baptiste Laloe
  • DEPOSITING AN ETCH STOP LAYER BEFORE A DUMMY CAP LAYER TO IMPROVE GATE PERFORMANCE
    Publication number: 20150249136
    Abstract: An improved method for fabricating a semiconductor device is provided. The method includes: depositing a dielectric layer on a substrate; depositing a first cap layer on the dielectric layer; depositing an etch stop layer on the dielectric layer; and depositing a dummy cap layer on the etch stop layer to form a partial gate structure. Also provided is a partially formed semiconductor device. The partially formed semiconductor device includes: a substrate; a dielectric layer on the substrate; a first cap layer on the dielectric layer; an etch stop layer on the dielectric layer; and a dummy cap layer on the etch stop layer forming a partial gate structure.
    Type: Application
    Filed: March 3, 2014
    Publication date: September 3, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Feng ZHOU, Tien-Ying LUO, Haiting WANG, Padmaja NAGAIAH, Jean-Baptiste LALOE, Isabelle Pauline FERAIN, Yong Meng LEE
  • Methods of forming replacement gate structures for NFET semiconductor devices and devices having such gate structures
    Patent number: 8803254
    Abstract: One illustrative gate structure for an NFET device includes a gate insulation layer formed above a semiconducting substrate, a first metal layer comprised of titanium nitride (TiN) positioned above the gate insulation layer, a second metal layer comprised of tantalum nitride (TaN) positioned above the first metal layer, a third metal layer comprised of titanium aluminum (TiAl) positioned above the second metal layer, a fourth metal layer comprised of an aluminum-containing material positioned above the third metal layer, a fifth metal layer comprised of titanium positioned above the fourth metal layer, and a layer of aluminum positioned above the fifth metal layer.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: August 12, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jean-Baptiste Laloe, Huang Liu, Wonwoo Kim
  • METHODS OF FORMING REPLACEMENT GATE STRUCTURES FOR NFET SEMICONDUCTOR DEVICES AND DEVICES HAVING SUCH GATE STRUCTURES
    Publication number: 20140145274
    Abstract: One illustrative gate structure for an NFET device includes a gate insulation layer formed above a semiconducting substrate, a first metal layer comprised of titanium nitride (TiN) positioned above the gate insulation layer, a second metal layer comprised of tantalum nitride (TaN) positioned above the first metal layer, a third metal layer comprised of titanium aluminum (TiAl) positioned above the second metal layer, a fourth metal layer comprised of an aluminum-containing material positioned above the third metal layer, a fifth metal layer comprised of titanium positioned above the fourth metal layer, and a layer of aluminum positioned above the fifth metal layer.
    Type: Application
    Filed: November 28, 2012
    Publication date: May 29, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Jean-Baptiste Laloe, Huang Liu, Wonwoo Kim