Abstract: A process and an apparatus for the granting of a resource in a system comprising at least two antonomous data processing units in which each unit can request the granting of the resource by means of an individual interface circuit. The interface circuits are coupled to a multiple conductor channel of the binary type which can assume first and second logic states. Each unit is also associated with a particular number and a priority level.

Abstract: In a system comprising data-processing units, some of which are masters and others of which are slaves, all the units are connected to a common bus via interface circuits. Only the master units are capable of acquiring instantaneous control of the bus by means of a resource allocation device. By utilizing a set of three basic control signals carried by the bus, three distinct addressing modes can be established: master-to-master, master-to-slave, general master-broadcasting to all units in accordance with a number of chronologies and transmission modes. In an alternative embodiment, substitutions of addresses can be performed directly on the bus.