Abstract: A modulation circuit uses pre-calculated and stored data to generate the modulated output. The modulator architecture uses pre-calculated, Gaussian filtered sine and cosine responses that are stored in a ROM (read-only memory) or other memory structure. The modulator output is then calculated as a simple sum of values read from the ROM and controlled by the input burst data stream.

Abstract: A power management bus for controlling power over multiple device subsystems includes a master power bus controller which transmits power management information to control one or more power resources through a transmit interface. The transmitted information is received at one or more receive interfaces. A broadcast message can be transmitted to control multiple power resources by subsystem, resource group and resource type. A single address message can be transmitted to control a single power resource. A power down can be initiated at any of the receive interfaces.

Abstract: A power management bus for controlling power over multiple device subsystems includes a master power bus controller which transmits power management information to control one or more power resources through a transmit interface. The transmitted information is received at one or more receive interfaces. A broadcast message can be transmitted to control multiple power resources by subsystem, resource group and resource type. A single address message can be transmitted to control a single power resource. A power down can be initiated at any of the receive interfaces.

Abstract: A tuning circuit uses a VCO with a trimming capacitor bank. The trimming capacitor bank is calibrated by logic to accommodate a desired frequency, fwanted. A search renders an initial control word that is accurate within one LSB. In a first embodiment, comparisons between the desired frequency and the upper and lower frequency bounds of the VCO with the trimming capacitor bank configured by the initial control word. The control word may be increased or decreased based on the comparisons. In a second embodiment, differences between the desired frequency and the actual frequency of the VCO, with the trimming capacitor bank configured by the initial control word, are compared to a threshold. The control word may be increased or decreased based on the comparison.

Abstract: A modulation circuit uses pre-calculated and stored data to generate the modulated output. The modulator architecture uses pre-calculated, Gaussian filtered sine and cosine responses that are stored in a ROM (read-only memory) or other memory structure. The modulator output is then calculated as a simple sum of values read from the ROM and controlled by the input burst data stream.

Abstract: A wireless telephone (10) including audio amplifier circuitry (20) that produces reduced “pop” noise in speakers such as in handsfree headsets (HS) is disclosed. The audio amplifier circuitry (20) includes an audio amplifier (22) that drives the headset speaker (HSS). A first transistor (26) has its source-drain path connected between an output (HSO) of the audio amplifier (22) and a power supply voltage (Vdd), and a second transistor (28) has its source-drain path connected between the amplifier output (HSO) and a reference voltage such as ground. The first and second transistors (26, 28) are controlled by control logic (24), in response to the state of various register locations (30) that indicate the powered-up and enabled state of the audio amplifier circuitry (20). Normal and automatic modes for the precharge control are available, with the automatic mode eliminating the need for the precharge enable register location (30d) being written during operation.

Abstract: A mobile communications device (50) includes a plurality of LDOs (30) for supplying a stable voltage to various circuits on the device. In a normal mode, the LDO's main bandgap voltage source (12) supplies a voltage to a main amplifier (16). During deep sleep mode, sleep logic (40) places the LDOs in a sleeping state, where a low current sleep bandgap voltage source (32) supplies a voltage to a smaller, sleep amplifier (36), which maintains a charge on capacitors (24, 26) for a fast transitions to a full ON state.

Abstract: A mobile communications device (50) includes a plurality of LDOs (30) for supplying a stable voltage to various circuits on the device. In a normal mode, the LDO's main bandgap voltage source (12) supplies a voltage to a main amplifier (16). During deep sleep mode, sleep logic (40) places the LDOs in a sleeping state, where a low current sleep bandgap voltage source (32) supplies a voltage to a smaller, sleep amplifier (36), which maintains a charge on capacitors (24, 26) for a fast transitions to a full ON state.

Abstract: An electronic integrated circuit includes a first signal (A1) generated by a first source block (10) and a second signal (B1) generated by a second source block (12). A variable delay circuit (18) detects a delay between said first and second signals in calibration mode and applies the delay to the first signal during normal operation of the circuit. A fixed delay buffer (32) may be used to apply a delay to the second signal to compensate for known delays associated with the variable delay circuit (18).

Abstract: A tuning circuit uses a VCO with a trimming capacitor bank. The trimming capacitor bank is calibrated by logic to accommodate a desired frequency, fwanted. A search renders an initial control word that is accurate within one LSB. In a first embodiment, comparisons between the desired frequency and the upper and lower frequency bounds of the VCO with the trimming capacitor bank configured by the initial control word. The control word may be increased or decreased based on the comparisons. In a second embodiment, differences between the desired frequency and the actual frequency of the VCO, with the trimming capacitor bank configured by the initial control word, are compared to a threshold. The control word may be increased or decreased based on the comparison.

Abstract: An electronic integrated circuit includes a first signal (A1) generated by a first source block (10) and a second signal (B1) generated by a second source block (12). A variable delay circuit (18) detects a delay between said first and second signals in calibration mode and applies the delay to the first signal during normal operation of the circuit. A fixed delay buffer (32) may be used to apply a delay to the second signal to compensate for known delays associated with the variable delay circuit (18).

Abstract: A wireless telephone (10) including audio amplifier circuitry (20) that produces reduced “pop” noise in speakers such as in handsfree headsets (HS) is disclosed. The audio amplifier circuitry (20) includes an audio amplifier (22) that drives the headset speaker (HSS). A first transistor (26) has its source-drain path connected between an output (HSO) of the audio amplifier (22) and a power supply voltage (Vdd), and a second transistor (28) has its source-drain path connected between the amplifier output (HSO) and a reference voltage such as ground. The first and second transistors (26, 28) are controlled by control logic (24), in response to the state of various register locations (30) that indicate the powered-up and enabled state of the audio amplifier circuitry (20). Normal and automatic modes for the precharge control are available, with the automatic mode eliminating the need for the precharge enable register location (30d) being written during operation.

Abstract: A mobile communications device (50) includes a plurality of LDOs (30) for supplying a stable voltage to various circuits on the device. In a normal mode, the LDO's main bandgap voltage source (12) supplies a voltage to a main amplifier (16). During deep sleep mode, sleep logic (40) places the LDOs in a sleeping state, where a low current sleep bandgap voltage source (32) supplies a voltage to a smaller, sleep amplifier (36), which maintains a charge on capacitors (24, 26) for a fast transitions to a full ON state.