Abstract: For certain operations executed in a multiprocessor system, the processors communicate with one another by exchanging requests and acknowledgements. To improve performance, the invention proposes a method by which the operations which require sending of multiple requests proceed without taking into account the reception of the acknowledgements. The total number of requests required is calculated and the number of acknowledgements received is counted. The end of the operation is conditioned by the equality of these two numbers. The invention also relates to a system for employing the method, and to the application of the method to dispatching.

Abstract: An apparatus for enabling communication of information between processes being carried out on a computing system. Each process is assigned a control block including a specialized memory element. A process being executed modifies the state of each memory element if it discovers any information of interest to processes awaiting execution. Before the next process is executed, the memory element in its control block is tested to find out if the previously-executed process left any information of interest.

Abstract: A system and method for computer process dispatching in a multiprogramming/multiprocessing environment is disclosed. Each process in the multiprogramming/multiprocessing computer system may be in one of four states at any given time as follows:1. Running -- the process is in control of the computer system and is directing the operation of the central processing unit (CPU);2. ready -- the process is ready to run as soon as it is given control of the CPU;3. waiting -- the process is waiting for an external event to occur so it can either resume running or enter the ready state;4. Suspended -- the process has been temporarily stopped (from a source external to the process).The dispatcher is a firmware/hardware structure that controls the first three states of the process--i.e. running, ready and waiting states.

Abstract: A data processing system having a common data bus to which access is gained by at least a control store, an arithmetic logic unit (ALU) and an emulator unit (EMU). The control store includes a microprogrammable switch for enabling either the EMU or the ALU to process instructions received on a common bus. Common opcode bits in the instruction are interpreted by either the ALU or the EMU and responded to thereby depending upon the state of a control register in the control store. The instructions are stored in a control store array in the control store coupled with the bus, and allows operation of either the ALU (native mode of operation) or the EMU (non-native mode of operation), dependent upon the microprogram's instruction in the control store thereby giving increased efficiency of operation of the system.