Abstract: A multiprogrammable/multiprocessing digital computer system having a process control block for each process in the system, wherein each process control block includes information which specifies the state of a processor at any given time. Associated with each process control block is a decor extension table having information to indicate whether a specified function, such as the emulation of another processor, may be executed in the system. A native mode instruction indicating a specified function for either one instruction or for a plurality of instructions, is first checked to determine proper format, after which a determination is made by means of the decor extension table, as to whether or not the system is capable of executing the specified function indicated by the native mode instruction.

Abstract: There is disclosed an input/output controller for an information processing system comprising a main memory, a central processing unit, a peripheral controller and a plurality of peripheral units coupled to the central processing unit. In particular, the input/output controller comprises a plurality of physical channels disposed between the peripheral controller and the central processing unit, a plurality of logical channels for transmitting information with the central processing unit, and each uniquely associated with one of the peripheral units. The main memory stores a first table including a physical channel entry containing informaton relative to the plurality of physical channels and a second table including a logical channel entry containing information relative to the plurality of peripheral units.

Abstract: The disclosure describes apparatus for handling detected errors in a data processing system. First means define and locate the detected errors and second means allow the attempted reexecution of the instruction being executed when the error is detected.

Abstract: The disclosure describes a data processing system including a program memory for storing a first instruction at a first address and a second instruction at a second address. The system includes a look-ahead feature in which the second instruction is stored in a buffer register while the first instruction is being stored in an execution register and is simultaneously being executed. A gate circuit controls the transmission of data between the buffer register and the execution register. If a third instruction having a third address is read into the program memory while the first instruction is being executed, the second and third addresses are compared. If the second and third addresses are identical, the gate circuit is inhibited and the second instruction is prevented from being transmitted to the execution register. Instead, the third instruction, or a portion thereof, is transmitted to the buffer and execution registers, so that the third instruction is executed in place of the second instruction.

Abstract: The disclosure describes a data processing system including a program memory for storing a first instruction at a first address and a second instruction at a second address. The system includes a look-ahead feature in which the second instruction is stored in a buffer register while the first instruction is being stored in an execution register and is simultaneously being executed. A gate circuit controls the transmission of data between the buffer register and the execution register. If a third instruction having a third address is read into the program memory while the first instruction is being executed, the second and third addresses are compared. If the second and third addresses are identical, the gate circuit is inhibited and the second instruction is prevented from being transmitted to the execution register. Instead, the third instruction or a portion thereof, is transmitted to the buffer and execution registers, so that the third instruction is executed in place of the second instruction.

Abstract: A sequence of microinstructions contained in the memory of a computer includes different sub-sequences of microinstructions which may not only begin but also end at different microinstructions of the sequence. When a sub-sequence is called, registers store the return address as well as the address of the last line of the sub-sequence and a comparator causes the computer to resume processing from the return address when the address of the line processed becomes identical to that of the stored address of the last line of the sub-sequence.