Abstract: A voltage regulator is disclosed which is connected to an external resistor. The voltage regulator provides a regulated voltage and includes first and second transistors. The first transistor has a power terminal connected to a power supply and the second transistor has an output terminal to output the regulated voltage. The second transistor is connected to the first transistor through a common terminal. The external resistive circuit is connected between the common terminal and the output terminal. An output current of the voltage regulator on the output terminal is equal to a sum of a first current passing through the resistive circuit and a second current passing through the second transistor. A control circuit is also provided which is connected to the input of the second transistor to turn on the second transistor for providing the second current when the first current exceeds a predetermined value.

Abstract: The invention relates to a voltage control means provided with a first and a second transistor T1 and T2 constituting a differential pair, the base of the first transistor T1 being intended to receive a reference voltage Vref, the base of the second transistor T2 being intended to receive a predetermined fraction Vs of a voltage applied to a power supply terminal VDD, and also provided with a first current mirror M1 and a second current mirror M2, each having its input connected to the collector of one of the transistors and its output connected to the collector of the other transistor, the output current of each mirror being K times larger than the input current.

Abstract: This invention relates to a reference voltage generator which provides for an optimum control of the output voltage as a function of temperature. The generator comprises two transistors, two current sources, two resistors, and a third transistor supplying current into a charge resistor. It also comprises, connected between the first and second transistors and the current sources, a pair of transistors whose bases are jointly connected to the base of the third transistor.

Abstract: An interface circuit for linking microprocessors, intended to limit the current (Iout) in the link (L1-L2) by inserting in the link the emitter-collector path of a first transistor (T.sub.1) which is in the saturated state during operation. This circuit includes a second transistor (T.sub.2) which has a geometry k times smaller than that of the first transistor (T.sub.1) and which is coupled to the first transistor (T.sub.1) so as to produce a copy (Iy) of the link current (Iout), and a base current generator (10) which produces an output current (Iz) which feeds the bases of the first and the second transistor (T.sub.1, T.sub.2), and which is a regressive function of the copy current (Iy), on the basis of a fixed reference current (I.sub.0). A pair of transistors (T.sub.3, T.sub.4), similar to the first and the second transistor (T.sub.1, T.sub.2) but connected to the link (L1-L2) in an inverted manner, provides protection for bidirectional operation.

Abstract: A differential circuit having a predefined voltage gain of the order of unity and with a high linearity includes a differential pair of input transistors fed by a DC current source (S) each through an emitter resistor having a resistance value R. A number p of forward biased junctions and a control branch of a current mirror are inserted in the emitter path of each of the input transistors to the current source. The output branch of each current mirror feeds a respective output resistor in series with a number k of forward biased junctions. A voltage gain of k/2(2+p) is obtained when the value of the output resistors is selected to be equal to k.R/(2+p). At the same time, compensation is provided for the linearity errors of the input transistors.

Abstract: A current source which provides a given ratio (G) of an output current (I) to an input current (i). The current source includes a first series combination of a first resistor (R.sub.1) connected in series with the main current path of a first transistor (T.sub.1) and a second series combination of a second resistor (R.sub.3) connected in series with the main current path of a second transistor (T.sub.2). The first and second transistors (T.sub.1, T.sub.2) form a current mirror circuit. A current equalizer is coupled to the current mirror circuit in such a way as to produce in the first series combination an equalizing voltage drop equal to ##EQU1## i.sub.s1 and i.sub.s2 denoting the characteristic current constants of the first and second transistors (T.sub.1, T.sub.2).