Patents by Inventor Jean Desuche

Jean Desuche has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7353417
    Abstract: A microcontroller is provided, which includes a control unit (UC), at least one digital to analog converter (DAC) as a peripheral of the said control unit, and a buffer register located between the said control unit and the said converter, receiving data and a first command to transfer the said data from the said control unit. The microcontroller includes means of synchronisation of the said converter including a register inserted between the said buffer register and the said converter, the said register receiving a second transfer command independent of the said control unit.
    Type: Grant
    Filed: January 19, 2005
    Date of Patent: April 1, 2008
    Assignee: Atmel Nantes SA
    Inventors: Jean Desuche, Etienne Bouin
  • Publication number: 20050248901
    Abstract: A microcontroller is provided, which includes a control unit (UC), at least one digital to analog converter (DAC) as a peripheral of the said control unit, and a buffer register located between the said control unit and the said converter, receiving data and a first command to transfer the said data from the said control unit. The microcontroller includes means of synchronisation of the said converter including a register inserted between the said buffer register and the said converter, the said register receiving a second transfer command independent of the said control unit.
    Type: Application
    Filed: January 19, 2005
    Publication date: November 10, 2005
    Applicant: Atmel Nantes SA
    Inventors: Jean Desuche, Etienne Bouin
  • Patent number: 5877639
    Abstract: A duration and frequency programmable electronic integrated pulse generator comprises an initialization circuit driven by a reference clock signal and an initialization/comparison signal and producing m initialization values, and a periodic count value coded on n bits. An address decoder module produces write-control bits, while a bits comparison matrix including n.times.m comparison cells each including a RAM and CAM memory cell write-addressable by the write-control bits. Each CAM cell stores a bit CAM.sub.ij of an initialization value and produces a complemented value CAM.sub.ij .sym.BL.sub.i , each RAM memory cell of address i, j produces a masking value M.sub.ij, and each comparison cell produces a value HIT.sub.ij =(CAM.sub.ij .sym.BL.sub.i)+M.sub.ij. All the cells of the same line of rank j are coupled by an OR function and produce, each output S.sub.j, a programmed pulse represented by the equation: ##EQU1## according to a harmonic periodic signal of the periodic count value.
    Type: Grant
    Filed: July 3, 1997
    Date of Patent: March 2, 1999
    Assignee: MHS
    Inventors: Michel Porcher, Stephane Chesnais, Jean Desuche