Abstract: The invention relates to a process for dynamically reconfiguring an information processing system (1), particularly a so-called “SMP” symmetric multiprocessor system. The process comprises a preliminary step for detecting a failure risk of one of the components of the system (CPU3). Following this detection, the system (1) is placed in a coherent, so-called “frozen” state in a first step with the aid of programs (J1-J4) executing specific tasks. A second step consists of reconfiguring the system by reallocating/de-allocating all or some of the components (CPU1-CPU4). In a third step, the component (CPU3) that presents a failure risk is isolated. The pending interruptions (4) are processed and the current tasks (6) are executed prior to the “freeze.” Likewise, the queues of tasks to be executed are purged prior to the “freeze.” Then, the subsequent tasks and interrupts are inhibited until a final step that consists of releasing the system (1).

Abstract: The lock architecture for a computer system comprises several processors (10, 11, 12, 13) such that each processor (10) requesting a resource of the system takes control of said resource if a first lock state indicates that said resource is free. The requesting processor is placed on active standby if a second lock state indicates that said resource is busy. A lock includes a first and second lock state. The first lock state corresponds to a null value, and the second lock state corresponds to a non-null value.

Abstract: The invention relates to a process for allocating physical memory locations in a multiprocessor data processing system comprising a non-uniform access memory unit distributed among a plurality of modules. Software applications are linked to a set of predefined memory allocation rules. When there is no entry for a virtual address in an address correspondence table, there is a generation of a page fault, and the allocation of a location in physical memory is carried out in accordance with a predefined rule as a function of the profile of the application and of the page fault type. The memory may be organized into segments and the segments subdivided into virtual address ranges, with the ranges associated with a specific memory allocation policy. In the case where there is an entry for a virtual address in an address correspondence table, the policy of the segment prevails.

Abstract: The invention relates to a process for accessing a storage area of a digital data processing machine (19) in a physical addressing mode the storage arena also being accessible in a virtual addressing mode by means of virtual addresses, each constituted by a logical page number (LPN) and a relative address (SPRA). A first logical page number (i) in question corresponds to a first given physical page number (q), and a second logical page number (i+1) contiguous to the first logical page number (i) in question corresponds to a second physical page number (s), not necessarily contiguous to the first given physical page number (q). The process is comprised of writing, at the address constituted by the first logical page number (i) in question and by a relative address having a first predetermined value, the second physical page number (s).

Abstract: A data processing machine with nonuniform memory access and cache coherency is constituted by a plurality of modules (10, 20, 40, 60), a given module (10) including a unit (6) to assure data coherence with other modules (20, 40, 60), characterized in that said unit (6) includes at least the following: a first register (81, 101) intended to contain a first physical address of the memory, a second register (82, 102) intended to contain a second physical address of the memory, first means (90, 95, 111, 121, 88, 92, 108) for measuring a quantity of activity relating to the data whose addresses are included between said first physical address and said second physical address, a third register (83, 93, 109) intended to contain a threshold value for measuring said quantity of activity, second means (91, 94, 112, 122) for detecting the exceeding of said threshold value by the quantity of activity measured by the first means.

Abstract: A machine with non-uniform memory access and cache coherency is constituted by a plurality of modules (10, 20, 40, 60), each module comprising a unit (6, 26, 46, 66), the unit (6) comprising at least one table (8) for managing local accesses to a memory part (5′) local to the module (10) and one table (9) for managing accesses to a memory part (25′, 45′, 65′) remote from the module (10), by means of a system bus (7). The machine comprises: a counter (81) of hits in the local memory part (5′) without a transaction with a remote module; a counter (82) of misses in the local memory part (5′) accompanied by at least one transaction with a remote module; a counter (91) of hits in the remote memory part (25′, 25′, 65′) without a transaction with a remote module; a counter (92) of misses in the remote memory part (25′, 45′, 65′) accompanied by at least one transaction with a remote module.

Abstract: A machine with non-uniform memory access and cache coherency is constituted by a plurality of modules (10, 20, 40, 60), each module comprising a unit (6, 26, 46, 66), the unit (6) comprising at least a first table (8) for managing local accesses to a memory part (5') local to the module (10) and a second table (9) for managing accesses to a memory part (25', 45', 65') remote from the module (10), by means of a system bus (7). The machine comprises:a counter (81) of replacements in the table (8) and a counter (83) of accesses to the first table (8);a counter (91) of replacements in the table (9) and a counter (93) of accesses to the second table (9).The replacement and access counters make it possible to optimize the size of the first and second tables (8) and (9), and/or the strategies for correspondence between virtual addresses and physical addresses.