Abstract: A method and digital system for testing scannable memory and combinational networks. The scannable memory is configurable into several scan chains. Each chain may have a different effective clock rate, as determined by respective clock enable signals. The method and digital system allow scan testing of digital circuits that use a single operational clock rate and several functional clock enable signals to effect slower lock operating rates. The digital system includes memory elements having scan enable and clock enable inputs.

Abstract: A method of testing an integrated circuit having core logic with two or more clock domains and at least one signal path originating in one clock domain and terminating in an other clock domain, each signal path having a source control element in the one clock domain and an associated destination control element in the other clock domain, each the control element being a scannable memory element, the method comprising the steps of, for each the control element shifting a test stimulus into all scannable elements in the core logic; placing an associated source control element in a hold mode for a predetermined number of clock cycles prior to a capture operation so that the source control element holds its output constant during the predetermined number of clock cycles; performing a capture operation for capturing the data output in response to the test stimulus by the control element and by all other scannable elements which are not control elements; maintaining an associated source control element in a hold mo

Abstract: A method of and apparatus for testing multi-port memory performs a shadow read to an adjacent memory cell concurrent with a write operation associated with typical read-write testing. In the presence of a bit wire short or a word wired short, the concurrent read of an adjacent memory cell will cause the value of that cell to be corrupted. The corrupted value is then found by the read-write testing. Consequently, the testing takes no longer than read-write testing. In addition, the testing scheme can be modified for memory with read only ports. An embodiment of the apparatus employs and exclusive OR gate on the least significant bit of the test row address line to generate the shadow read address.