Abstract: A sign-off method for use in verifying of embedded test structures in a circuit design extracts a description of all embedded test structures from a circuit description to create a test connection map file, and verifies the connections of the test structures to circuit pins or nets, creates verification configuration files for use, in performing a sign-off verification of the circuit, for a circuit containing logic test structures, verifies that each logic test structure complies with logic test design rules and creates logic test vectors and a reference signature, performs a formal verification and a static timing analysis of the circuit, generates a sign-off simulation test bench for each test structure using the verification configuration files and the test connection map file, executes the test benches to simulate all test structures in the circuit; and creates manufacturing test patterns.

Abstract: An embedded test, chip design utility is an ease-of-use utility for assisting a circuit designer in quickly implementing a circuit embedded test design flow. Using the utility, a designer transforms a design netlist to include embedded test structures. The utility automatically builds a workspace containing a predetermined repository structure and design environment, generates control files for executing design automation tools that operate within the design flow, and encapsulates the data so as to be self-contained and easily transferable to other design teams.

Abstract: A method of scan testing an integrated circuit to provide real time identification of a block of test patterns having at least one failing test pattern comprises performing a number of test operations and storing a test response signature corresponding to each block of test patterns into a signature register; replacing the test response signature in the signature register with a test block expected signature; identifying the block as a failing test block when the test response signature is different from the test block expected signature; and repeating preceding steps until the test is complete.

Abstract: A method of scan testing an integrated circuit to provide real time identification of a block of test patterns having at least one failing test pattern comprises performing a number of test operations and storing a test response signature corresponding to each block of test patterns into a signature register; replacing the test response signature in the signature register with a test block expected signature; identifying the block as a failing test block when the test response signature is different from the test block expected signature; and repeating preceding steps until the test is complete.

Abstract: A method of collecting failure information when testing a memory comprises performing a test of the memory according to a test algorithm, and, while performing the test, counting failure events which occur after a predetermined number of masked events; stopping the test upon occurrence of a stopping criterion which comprises one of occurrence of a first failure event, a change of a test operation; a change of a memory column address; a change of a memory row address; a change of a memory bank address; and a change of a test algorithm phase; and storing failure information.

Abstract: A test access circuit (TAC) for use in controlling test resources including child test access circuits (TACs) and/or test controllers, in an integrated circuit, comprises an enable input for enabling or disabling access to the test resources, a test port associated with each test resource, each test port including a test port enable output for connection to an enable input of an associated test resource; and an input for receiving a serial output of the associated test resource; and means for selecting a test resource for communication therewith.

Abstract: One aspect of the invention is generally defined as a method of designing an integrated circuit for distributing test clock signals to embedded cores having at least one core functional clock input, the method comprising, for each core, providing a clock gating circuit for selectively disabling a core functional clock signal applied to a core primary clock input; and providing a core clock selection circuit for each secondary core functional clock input for selecting one of a core functional clock signal output by the gating circuit and a core test clock signal and applying a selected signal to the each secondary core functional clock input.

Abstract: A method for use in the hierarchical design of integrated circuits having at least one module, each the module having functional memory elements and combinational logic, the method comprising reading in a description of the circuit; replacing the description of each functional memory element of the modules with a description of a scannable memory element configurable in scan mode and capture mode; partitioning each module into an internal partition and a peripheral partition by converting the description of selected scannable memory elements into a description of peripheral scannable memory elements which are configurable in an internal test mode, an external test mode and a normal operation mode; modifying the description of modules in the circuit description so as to arrange the memory elements into scan chains in which peripheral and internal scannable memory elements of each module are controlled by an associated module test controller when configured in internal test mode; and peripheral scannable memory

Abstract: A program product for use in generating test benches for verifying test structures embedded in a circuit, comprises a verification specification processor for parsing a verification specification containing test specifications for selected test structures and a test bench generator for each of one or more types of embedded test structures, each test bench generator being operable to process a test structure specification of a test structure of a corresponding test structure type and generate a test bench using data contained in said test specifications of said verification specification, data contained in said test structure specification and data contained in a test connection specification.

Abstract: One aspect of the invention is generally defined as a method of designing an integrated circuit for distributing test clock signals to embedded cores having at least one core functional clock input, the method comprising, for each core, providing a clock gating circuit for selectively disabling a core functional clock signal applied to a core primary clock input; and providing a core clock selection circuit for each secondary core functional clock input for selecting one of a core functional clock signal output by the gating circuit and a core test clock signal and applying a selected signal to the each secondary core functional clock input.

Abstract: A method of controlling access to Intellectual Property (IP) -blocks embedded in a circuit comprises decoding a circuit usage rights file associated with the circuit and delineating usage rights associated with the IP blocks, determining from the circuit usage rights file whether access to an IP block to be accessed is permitted; and accessing the IP block only if access is permitted.

Abstract: A sign-off method for use in verifying of embedded test structures in a circuit design extracts a description of all embedded test structures from a circuit description to create a test connection map file, and verifies the connections of the test structures to circuit pins or nets, creates verification configuration files for use, in performing a sign-off verification of the circuit, for a circuit containing logic test structures, verifies that each logic test structure complies with logic test design rules and creates logic test vectors and a reference signature, performs a formal verification and a static timing analysis of the circuit, generates a sign-off simulation test bench for each test structure using the verification configuration files and the test connection map file, executes the test benches to simulate all test structures in the circuit; and creates manufacturing test patterns.

Abstract: An embedded test, chip design utility is an ease-of-use utility for assisting a circuit designer in quickly implementing a circuit embedded test design flow. Using the utility, a designer transforms a design netlist to include embedded test structures. The utility automatically builds a workspace containing a predetermined repository structure and design environment, generates control files for executing design automation tools that operate within the design flow, and encapsulates the data so as to be self-contained and easily transferable to other design teams.

Abstract: A method of designing integrated circuits having an hierarchical structure for quiescent current testing, and the circuit which results therefrom is disclosed. The method comprises analyzing each of one or more selected hierarchical blocks independently of other selected blocks identify any circuit states of each block which could result in elevated quiescent current levels during quiescent current testing of the circuit, the analysis beginning with blocks at a lowest level of hierarchy and proceeding in sequence through each level of design hierarchy to a highest level of hierarchy containing a top-level block; and calculating a fault coverage for each selected block.

Abstract: A number of fault injection circuits and corresponding methods for injecting correlated, uncorrelated, non-persistent and persisting faults at the primary outputs of boundary scan cells are disclosed. Fault data is loaded in the boundary scan cell update latch of all boundary scan cells at which a fault is to be injected. The fault injection circuits generate a fault inject signal which is applied to the control input of the standard cell output selector, an active signal causing the content of the update latch to be applied to the cell primary output. In order to provide for scan testing of the fault injection circuitry, the boundary scan cell shift and update latches and the fault flag latch (if employed) are provided with hold capability so that the contents of these elements can be controlled and their input captured in accordance with standard scan testing techniques.

Abstract: A method for at-speed testing high-performance digital systems and circuits having combinational logic and memory elements that may be both scannable and non-scannable is performed by enabling at least two clock pulses during a capture sequence following a shift sequence. The method provides for initialization of any non-scannable memory elements via the scannable memory elements at the beginning of the test before an at-speed test is performed. During initialization, control logic generates a signal to disable the generation of system clock pulses for capture. Instead, only one clock cycle derived from the test clock or a system clock is generated to initialize the non-scannable elements. The number of shift sequences required depends on the maximum number of non-scannable elements that must be traversed between two scannable memory elements. During the same initialization period, the output response analyzer is disabled since unknown data values will present in the stream of data shifted out.

Abstract: In a circuit with multiple Test Access Port (TAP) interfaces, the TAPs are arranged into groups, with secondary TAPs in one or more groups and a master TAP in another group, the master TAP having an instruction register with bits for storing a group selection code; a Test Data Output (TDO) circuit responsive to the group selection code connects the group TDO of one of the groups to the circuit TDO; and, for each secondary TAP group, a group Test Data Input (TDI) circuit responsive to a shift state signal for selectively connecting the group TDI to the circuit TDI or to the output of a padding register having its input connected to the circuit TDI, and its output connected to an input of the group TDI circuit; and a group TMS circuit responsive to a predetermined TAP selection code associated with the group for producing a group TMS signal for each TAP in the group.

Abstract: A method for at-speed scan testing of circuits having scannable memory elements which source multi-cycle paths having propagation delays that are longer than the period of a system clock used during normal operation comprises loading a test stimulus into the scannable memory elements; performing a capture operation, including configuring in capture mode throughout the capture operation, non-source memory elements and multi-cycle path source memory elements which have a predetermined maximum capture clock rate which is the same as or higher than the clock rate of the capture clock; and configuring in a hold mode during all but the last cycle of the capture operation and in capture mode for the last cycle, source memory elements which have a predetermined maximum capture clock rate which is lower than the clock rate of the capture clock; applying at least two clock cycles of the capture clock; and unloading test response data captured by said scannable memory elements.

Abstract: An improvement in a method of testing a digital circuit or system, having a plurality of scannable memory elements, in accordance with conventional BIST methods in which, at a reference clock, a test stimulus is shifted into the memory elements, the response of the elements is captured and the captured data is shifted out of the elements and analyzed, the improvement comprising controlling the average power consumption of the circuit during the test by suppressing clock pulses from the reference clock during phases of the test that do not require the maximum level of activity or in which the performance of the circuit is not to be evaluated; and, suppressing no clock pulses from the reference clock in phases of the test in which the performance of the circuit is to be evaluated, so that the conditions are substantially as those of normal mode of operation of the circuit.

Abstract: A method of testing the core logic in a digital system, the method having a sequence of test operations including a shift-in operation in which a test stimulus is shifted into scanable memory elements in the core logic, a capture operation in which data in the memory elements is captured, and a shift-out operation in which captured data is shifted out of the core logic for analysis, comprises the improvement of, for each the test operation, concurrently enabling the domain clock of each clock domain in the core logic at the beginning of each test operation, performing the test operation in each domain and disabling the domain clock at the end of each test operation in each domain. The method allows all of the clock domains, including signal paths which traverse domain boundaries and/or have multi-cycle paths to be tested concurrently and at their respective functional clock rate of each clock.