Abstract: Some embodiments of the present disclosure are directed to a method by a device for detecting an approaching vehicle. The method includes recording a sound waveform, and determining whether the recorded sound waveform is associated with a vehicle. A further determination is made whether the vehicle is approaching the device, which recorded the sound waveform, based on determining that the recorded sound waveform is indeed associated with a vehicle. An alert is generated which indicates that the vehicle is approaching the device, based on the determination that the vehicle is approaching.

Abstract: Some embodiments of the present disclosure are directed to a method by a device for detecting an approaching vehicle. The method includes recording a sound waveform, and determining whether the recorded sound waveform is associated with a vehicle. A further determination is made whether the vehicle is approaching the device, which recorded the sound waveform, based on determining that the recorded sound waveform is indeed associated with a vehicle. An alert is generated which indicates that the vehicle is approaching the device, based on the determination that the vehicle is approaching.

Abstract: A method and system for associating system events with program instructions in a computer system are disclosed. A program is executed or manually processed to identify instructions which cause system events. Then, markers are inserted into the program, each marker being associated with at least one of the identified instructions. When the program is executed, system events which occur during the execution are associated with program instructions using the markers.

Abstract: A method and system for flexible prefetching of data and/or instructions for applications are described. A prefetching mechanism monitors program instructions and tag information associated with the instructions. The tag information is used to determine when a prefetch operation is desirable. The prefetching mechanism then requests data and/or instructions. Furthermore, the prefetching mechanism determines when entry into a different execution phase of an application program occurs, and executes a different prefetching policy based on the application's program instructions and tag information for that execution phase as well as profile information from previous executions of the application in that execution phase.

Abstract: Systems and methods according to the present invention provide techniques which modify programs having barrier statements. Dependence relations between statements, and enforcement associations between the barrier statements and the dependence relations, in the program are identified. The dependence relations are classified as being either enforceable by point-to-point synchronization or not enforceable by point-to-point synchronization. A subset of the barrier statements, which will enforce those dependence relations that are unenforceable by point-to-point synchronization, are determined. Other(s) of the barrier statements are replaced with a point-to-point synchronization routine.

Abstract: Methods and systems for prioritizing virtual network interface controllers (VNICs) are described. Each VNIC is assigned a priority level and a maximum current priority level associated with VNICs which are requesting service is determined. Fairness is enforced by using a round robin approach to selection among those currently requesting VNICs which have the same, maximum current priority level.

Abstract: A method and system for selectively applying one of a plurality of different memory coherence protocols are described. When an application is executed to generate a memory access transaction, a table can be evaluated to determine whether the transaction should be processed in accordance with a first memory coherence protocol or a second memory coherence protocol. Then, the transaction can be processed according to the selected memory coherence protocol. Alternatively, or in conjunction therewith, the application can be modified to execute more efficiently on a particular memory coherence protocol.

Abstract: Methods and systems for communicating between network interface controllers (NICs) in networked systems are described. Enhanced command functionality for NICs include the ability to perform sequences of operations and/or conditional operations. Messages can be used to communicate embedded commands which are interpreted by NICs to enhance their functionality.

Abstract: Methods and systems for performing direct memory access (DMA) transfers are described. An invalidate queue (or other storage device) contains an entry associated with a DMA transfer in progress. If the invalidate queue detects an invalidation of a memory page associated with that entry, then it is marked invalid. If the entry is marked invalid during the DMA transfer, then that DMA transfer is aborted. This enables, among other things, DMA transfers to unpinned virtual memory.

Abstract: A method of scheduling optional instructions in a compiler targets a processor. The scheduling includes indicating a limit on the additional processor computations that are available for executing an optional code, generating one or more required instructions corresponding to a source code and one or more optional instructions corresponding to the optional code used with the source code and scheduling all of the one or more required instructions with as many of the one or more optional instructions as possible without exceeding the indicated limit on the additional processor computations for executing the optional code.

Abstract: A technique includes identifying an address of a head end of a queue and monitoring a coherent interconnect to identify a data transfer that is communicated by a producer, which targets the address. The technique includes storing the data of the data transfer in the queue and selectively storing at least a portion of the data in a head-of-queue cache memory based at least in part on whether the monitoring identifies the address. At least a portion of the data is selectively retrieved from the head-of-queue cache memory instead of from the queue for transmission to a consumer.

Abstract: Disclosed are embodiments of a compiler, methods, and system for resource-aware scheduling of instructions. A list scheduling approach is augmented to take into account resource constraints when determining priority for scheduling of instructions. Other embodiments are also described and claimed.

Abstract: An embodiment of a vector processor includes a vector control and distribution unit and lanes. In operation, the vector control and distribution unit receives vector instructions, decomposes the vector instructions into vector element operations, and forwards the vector element operations for execution. Each lane proceeds to execute vector element operations independently of other lanes. An embodiment of a vector processing system includes a host processor, a main memory, and a vector processor. In operation, the host processor forwards vector instructions and vector data to the vector processor for processing. The vector control and distribution unit decomposes the vector instructions into vector element operations and forwards the vector element operations to the lanes. Each lane proceeds to execute vector element operations that the lane receives on a portion of the vector data independent of execution of instructions executing in other lanes.

Abstract: Techniques for modifying applications to implement memory allocation are disclosed. The application is executed using a default memory allocation scheme. A log is generated that identifies which memory addresses are requested by which instructions of the application. The log is evaluated to identify changes to be made to the default memory allocation scheme and, after execution, the application is modified by adding instructions to implement the identified changes.

Abstract: According to an exemplary embodiment of the present invention, a method for loading data from at least one memory device includes the steps of loading a first value from a first memory location of the at least one memory device, determining a second memory location based on the first value and loading a second value from the second memory location of the at least one memory device, wherein the step of loading a first value is performed by a first processing unit and wherein the steps of determining a second memory location and loading a second value are performed by at least one other processing unit.

Abstract: Methods and systems for performing direct memory access (DMA) transfers are described. An invalidate queue (or other storage device) contains an entry associated with a DMA transfer in progress. If the invalidate queue detects an invalidation of a memory page associated with that entry, then it is marked invalid. If the entry is marked invalid during the DMA transfer, then that DMA transfer is aborted. This enables, among other things, DMA transfers to unpinned virtual memory.

Abstract: One embodiment relates to a computer apparatus including at least a microprocessor having an address space, an accelerator configured to cooperatively execute a program with the microprocessor, and a data register in the accelerator. The data register in the accelerator is mapped into the memory address space of the microprocessor. Other embodiments are also disclosed.

Abstract: Methods and systems for caching data from a head end of a queue are described. The cached data can then be selectively forwarded from the data producer to the data consumer upon request.

Abstract: The present invention is a method of and system for program thread synchronization. In accordance with an embodiment of the invention, a method of synchronizing program threads for one or more processors is provided. An instruction cache line for is determined each of a plurality of program threads to be synchronized. For each processor executing one or more of the threads to be synchronized, execution of the thread is halted at a barrier by rendering the determined instruction cache line unavailable. Execution of the threads resumes by rendering the determined instruction cache lines available.

Abstract: The present invention is a method of and system for program thread synchronization. In accordance with an embodiment of the invention, a method of synchronizing program threads for one or more processors is provided. An address for data for each of a plurality of program threads to be synchronized is determined. For each processor executing one or more of the threads to be synchronized, execution of the thread is halted at a barrier by attempting a data operation to the determined address and the address being unavailable. Execution of the threads is resumed.