Abstract: A system and method of minimizing the context saved when the processing unit is disclosed. The kernel attempts to save time and memory by reducing or eliminating the amount of context that is saved or restored in certain situations. Specifically, if there is no currently executing, the kernel does not save any context before switching to another task. Similarly, if there is no new task to execute, the kernel does not restore any context before making the context switch. Rather, the kernel applies a lightweight context. In some embodiments, the idle context uses the ISR stack rather than having a dedicated stack. This system and method reduces the time required for certain context switches and also saves memory.

Abstract: A novel method of reporting pertinent information in the event of an error during the execution of a software application is disclosed. The software application includes one or more error reporting structures, which are used to store the pertinent information for each error that is encountered. The pertinent information may include, for example, the file name, the function name, the line number within the function, and others. In some embodiments, a macro is used to populate one or more fields of the error reporting structure. Various methods of identifying the location of the error reporting structure are also disclosed.

Abstract: A novel method of providing a locking mechanism which supports multiple operations rights is disclosed. The locking mechanism includes a policy aspect which defines which operations are allowed to access the common resource concurrently. The locking mechanism also includes the ability to allow predetermined number of tasks to access the common resource simultaneously. Furthermore, additional operations can be easily and quickly added to the mechanism.

Abstract: A novel method of reporting pertinent information in the event of an error during the execution of a software application is disclosed. The software application includes one or more error reporting structures, which are used to store the pertinent information for each error that is encountered. The pertinent information may include, for example, the file name, the function name, the line number within the function, and others. In some embodiments, a macro is used to populate one or more fields of the error reporting structure. Various methods of identifying the location of the error reporting structure are also disclosed.

Abstract: A novel method of providing a locking mechanism which supports multiple operations rights is disclosed. The locking mechanism includes a policy aspect which defines which operations are allowed to access the common resource concurrently. The locking mechanism also includes the ability to allow predetermined number of tasks to access the common resource simultaneously. Furthermore, additional operations can be easily and quickly added to the mechanism.

Abstract: The invention proposes a simple method for controlling distributed functional units (FU) in a system. It offloads the main system processor from intermediate status monitoring. The sequencer controlled system comprises a plurality of functional units, a processor operatively coupled to the plurality of functional units through a bus, a sequencer having a set of registers, and an interrupt source register configured for interrupt polling. The registers are configured to control the timing of at least one operation of the functional units with stored instructions for each of the functional units. The processor sets up at least some of the registers through the bus for the initial configuration and the sequencer is activated by the processor.

Abstract: The invention proposes a simple method for controlling distributed functional units (FU) in a system. It offloads the main system processor from intermediate status monitoring. The sequencer controlled system comprises a plurality of functional units, a processor operatively coupled to the plurality of functional units through a bus, a sequencer having a set of registers, and an interrupt source register configured for interrupt polling. The registers are configured to control the timing of at least one operation of the functional units with stored instructions for each of the functional units. The processor sets up at least some of the registers through the bus for the initial configuration and the sequencer is activated by the processor.