Patents by Inventor Jean-Francois Gilbert

Jean-Francois Gilbert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of testing a semiconductor-on-insulator structure and application of said test to the fabrication of such a structure
    Patent number: 9698063
    Abstract: The invention concerns a method of testing a semiconductor-on-insulator type structure comprising a support substrate, a dielectric layer having a thickness of less than 50 nm and a semiconductor layer, the structure comprising a bonding interface between the dielectric layer and the support substrate or the semiconductor layer or inside the dielectric layer, characterized in that it comprises measuring the charge to breakdown (QBD) of the dielectric layer and in that information is deduced from the measurement relating to the hydrogen concentration in the layer and/or at the bonding interface. The invention also concerns a method of fabricating a batch of semiconductor-on-insulator type structures including carrying out the test on a sample structure from the batch.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: July 4, 2017
    Assignee: SOITEC
    Inventors: Patrick Reynaud, Walter Schwarzenbach, Konstantin Bourdelle, Jean-Francois Gilbert
  • METHOD OF TESTING A SEMICONDUCTOR ON INSULATOR STRUCTURE AND APPLICATION OF SAID TEST TO THE FABRICATION OF SUCH A STRUCTURE
    Publication number: 20150014822
    Abstract: The invention concerns a method of testing a semiconductor on insulator type structure comprising a support substrate, a dielectric layer having a thickness of less than 50 nm and a semiconductor layer, the structure comprising a bonding interface between the dielectric layer and the support substrate or the semiconductor layer or inside the dielectric layer, characterized in that it comprises measuring the charge to breakdown (QBD) of the dielectric layer and in that information is deduced from the measurement relating to the hydrogen concentration in the layer and/or at the bonding interface. The invention also concerns a method of fabricating a batch of semiconductor on insulator type structures including carrying out the test on a sample structure from the batch.
    Type: Application
    Filed: February 18, 2013
    Publication date: January 15, 2015
    Applicant: SOITEC
    Inventors: Patrick Reynaud, Walter Schwarzenbach, Konstantin Bourdelle, Jean-Francois Gilbert