Abstract: A circuit (200) for protection against voltage or current spikes receives an initial clock signal (CI) and transmits at least one resultant clock signal (CN1, CN2, CP1, CP2) to a downstream circuit. This resultant clock signal is inactive if a random voltage or current spike appears upstream. This averts the possibility of disturbing the operation of the downstream circuit. Application to the protection of clock circuits for integrated circuits.

Abstract: Disclosed are protection circuitry, and methods of operating the same, for use with clock circuits associated with integrated circuits (ICs). According to one exemplary embodiment, the protection circuitry is operable to generate at least two intermediate clock signals as a function of a received clock signal, and process the at least two intermediate clock signals to (i) cause an output of the protection circuitry to enter a high-impedance state when the at least two intermediate clock signals are different, and (ii) generate a resultant clock signal at the output of the protection circuitry equal to the received clock signal when the at least two intermediate clock signals are identical.

Abstract: A circuit (200) for protection against voltage or current spikes receives an initial clock signal (CI) and transmits at least one resultant clock signal (CN1, CN2, CP1, CP2) to a downstream circuit. This resultant clock signal is inactive if a random voltage or current spike appears upstream. This averts the possibility of disturbing the operation of the downstream circuit. Application to the protection of clock circuits for integrated circuits.

Abstract: A micro-pipeline type asynchronous circuit and a method for detecting and correcting soft error. The asynchronous circuit records in a first recording unit a signal output by a calculation unit and then records in a second recording unit the same signal delayed by at least the duration of the pulse of a soft error. The recorded signals then are compared in a comparer circuit. If they are identical, no soft error has been detected and the output signal is recorded after another delay that is longer than the pulse duration of the soft error, and a request signal is transmitted to a control unit of a next logic stage with a delay twice as long as the pulse duration of a soft error.

Abstract: A micro-pipeline type asynchronous circuit and a method for detecting and correcting soft error. The asynchronous circuit records in a first recording unit a signal output by a calculation unit and then records in a second recording unit the same signal delayed by at least the duration of the pulse of a soft error. The recorded signals then are compared in a comparer circuit. If they are identical, no soft error has been detected and the output signal is recorded after another delay that is longer than the pulse duration of the soft error, and a request signal is transmitted to a control unit of a next logic stage with a delay twice as long as the pulse duration of a soft error.