Abstract: An architecture for a special purpose microprocessor particularly adapted for coupling a computer to its associated peripheral devices or to transmission lines. To minimize restrictions on the speed of data exchange, the present microprocessor allows the following to take place simultaneously: (1) general coupling of the computer and associated transmission lines and, more particularly, execution of instructions for coupling, shifting, or indirect conditional branching; and (2) the performance of arithmetic and/or logic operations on data which is exchanged between the computer and the associated transmission or peripheral lines. The present microprocessor executes microinstructions which are stored in a control memory. The format of the microinstructions is such that information in various zones controls the functions to be simultaneously performed.