Abstract: A method of emulation or functional testing of a first microprocessor in its functional environment including one or several peripherals and at least one internal bus of communication between this first microprocessor and its peripherals, from a second microprocessor, consisting of deactivating the first microprocessor, using the communication bus(es) to communicate between the two microprocessors and the peripheral(s), and activating the second microprocessor, wherein the first microprocessor communicates with the second microprocessor over a series link and wherein the second microprocessor is realized by a simulation model.

Abstract: A mixer receiving a first analog signal and a first digital signal, corresponding to a succession, at a first frequency, of first messages each comprising a first number of bits, and providing a second analog signal, comprises an analog-to-digital converter of the first analog signal into a second digital signal, corresponding to a succession, at a second frequency greater than the first one, of second messages having a second number of bits smaller than the first one; a digital-to-digital converter of the second digital signal into a third one corresponding to a succession, at the second frequency, of third messages having the first number of bits; an interpolation unit providing a fourth digital signal corresponding to a succession, at the second frequency, of fourth messages having the first number of bits; an adder providing the sum of the third and fourth digital signals; and an output digital-to-analog converter.

Abstract: A method and a circuit for controlling the access to all or part of the content of a memory that is integrated with a microprocessor, a priority-holding interrupt, at least one register of keys, and at least one access control algorithm contained in a second auxiliary memory are used. The content of at least one also integrated storage element and the content of the key register, the content of the auxiliary memory being programmable only once.

Abstract: An integrated circuit -comprising volatile memory elements, interface circuits connected to the volatile memory elements and, possibly, logic circuits not connected to the volatile memory elements and comprising first, second, and possibly third separate power supplies, the first power supply being connected to the volatile memory elements, the second power supply being connected to the interface circuits with the memory elements, and the third power supply being connected to other logic circuits.

Abstract: An integrated circuit comprising volatile memory elements, interface circuits connected to the volatile memory elements and, possibly, logic circuits not connected to the volatile memory elements and comprising first, second, and possibly third separate power supplies, the first power supply being connected to the volatile memory elements, the second power supply being connected to the interface circuits with the memory elements, and the third power supply being connected to other logic circuits.

Abstract: A mixer receiving a first analog signal and a first digital signal, corresponding to a succession, at a first frequency, of first messages each comprising a first number of bits, and providing a second analog signal, comprises an analog-to-digital converter of the first analog signal into a second digital signal, corresponding to a succession, at a second frequency greater than the first one, of second messages having a second number of bits smaller than the first one; a digital-to-digital converter of the second digital signal into a third one corresponding to a succession, at the second frequency, of third messages having the first number of bits; an interpolation unit providing a fourth digital signal corresponding to a succession, at the second frequency, of fourth messages having the first number of bits; an adder providing the sum of the third and fourth digital signals; and an output digital-to-analog converter.

Abstract: An integrated circuit comprising volatile memory elements, interface circuits connected to the volatile memory elements and, possibly, logic circuits not connected to the volatile memory elements and comprising first, second, and possibly third separate power supplies, the first power supply being connected to the volatile memory elements, the second power supply being connected to the interface circuits with the memory elements, and the third power supply being connected to other logic circuits.

Abstract: A method of emulation or functional testing of a first microprocessor in its functional environment including one or several peripherals and at least one internal bus of communication between this first microprocessor and its peripherals, from a second microprocessor, consisting of deactivating the first microprocessor, using the communication bus(es) to communicate between the two microprocessors and the peripheral(s), and activating the second microprocessor, wherein the first microprocessor communicates with the second microprocessor over a series link and wherein the second microprocessor is realized by a simulation model.

Abstract: A method and a circuit for controlling the access to all or part of the content of a first memory integrated with a microprocessor, consisting of using a priority-holding interrupt, of using at least one register of keys, and of applying at least one access control algorithm contained in a second auxiliary memory and using the content of at least one also integrated storage element and the content of the key register, the content of the auxiliary memory being programmable only once.