Patents by Inventor Jean Gueneau de Mussy

Jean Gueneau de Mussy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060160353
    Abstract: Damascene stacks for use in semiconductor devices and methods for making such stacks are disclosed. An example damascene stack includes a substantially planar lower liner layer and a patterned sacrificial dielectric layer disposed on top of the lower liner layer, where the patterned sacrificial dielectric layer includes an interconnect structure of the damascene stack. The example damascene stack further includes a substantially planar upper liner layer disposed on top of the patterned sacrificial dielectric layer, where the upper liner layer being formed of a material that is resistant to etching by a first etch compound. There is at least one plug-hole in the upper liner layer, where the at least one plug-hole is (i) adjacent to the interconnect structure and (ii) formed by locally converting a portion of the upper liner layer to be etchable by the first etch compound and removing the locally converted portion of the upper liner layer using the first etch compound.
    Type: Application
    Filed: March 16, 2006
    Publication date: July 20, 2006
    Applicant: Interuniversitair Microelektronica Centrum (IMEC vzw)
    Inventors: Jean Gueneau de Mussy, Gerald Beyer, Karen Maex
  • Publication number: 20050074960
    Abstract: Method for the production of airgaps in a semiconductor device, the semiconductor device comprising a stack of layers, the stack of layers comprising at least one iteration of a sub-stack of layers.
    Type: Application
    Filed: September 30, 2004
    Publication date: April 7, 2005
    Applicant: Interuniversitair Microelektronica Centrum (IMEC vzw)
    Inventors: Jean Gueneau de Mussy, Gerald Beyer, Karen Maex
  • Publication number: 20050074961
    Abstract: A method for the production of airgaps in a semiconductor device and device produced therefrom. The formation of airgaps is accomplished, in part, by chemically and/or mechanically changing the properties of a first dielectric layer locally, such that at least part of said first dielectric layer is converted locally and becomes etchable by a first etching substance. The local conversion of the dielectric material may be achieved during anisotropic etching of the material in oxygen containing plasma or ex-situ by performing an oxidizing step (e.g., a UV/ozone treatment or supercritical carbon dioxide with addition of an oxidizer). Formation of airgaps is achieved after creation of conductive lines and, alternatively, a barrier layer by a first etching substance. The airgaps are formed in a dual damascene structure, near the vias and/or the trenches of the damascene structure.
    Type: Application
    Filed: September 30, 2004
    Publication date: April 7, 2005
    Applicants: Interuniversitair Microelektronica Centrum (IMEC vzw), Texas Instruments, Inc.
    Inventors: Gerald Beyer, Jean Gueneau de Mussy, Karen Maex, Victor Sutcliffe