Patents by Inventor Jean-Jacques Fagot
Jean-Jacques Fagot has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11818901Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.Type: GrantFiled: September 29, 2021Date of Patent: November 14, 2023Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SASInventors: Philippe Boivin, Jean Jacques Fagot, Emmanuel Petitprez, Emeline Souchier, Olivier Weber
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Patent number: 11329067Abstract: An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.Type: GrantFiled: June 11, 2020Date of Patent: May 10, 2022Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SASInventors: Jean-Jacques Fagot, Philippe Boivin, Franck Arnaud
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Publication number: 20220020816Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.Type: ApplicationFiled: September 29, 2021Publication date: January 20, 2022Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SASInventors: Philippe BOIVIN, Jean Jacques FAGOT, Emmanuel PETITPREZ, Emeline SOUCHIER, Olivier WEBER
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Patent number: 11152430Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.Type: GrantFiled: April 4, 2019Date of Patent: October 19, 2021Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SASInventors: Philippe Boivin, Jean Jacques Fagot, Emmanuel Petitprez, Emeline Souchier, Olivier Weber
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Patent number: 10998378Abstract: A MOS transistor with two vertical gates is formed within a substrate zone of a semiconductor substrate doped with a first type of conductivity and separated from a remaining portion of the substrate by two first parallel trenches extending in a first direction. An isolated gate region rests on each flank of the substrate zone and on a portion of the bottom of the corresponding trench to form the two vertical gates. At least one gate connection region electrically connects the two vertical gates. A first buried region located under the substrate zone is doped with a second type of conductivity to form a first conduction electrode of the MOS transistor. A second region doped with the second type of conductivity is located at the surface of the substrate zone to form a second conduction electrode of the MOS transistor.Type: GrantFiled: August 16, 2019Date of Patent: May 4, 2021Assignee: STMicroelectronics (Rousset) SASInventors: Philippe Boivin, Jean-Jacques Fagot
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Publication number: 20200303423Abstract: An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.Type: ApplicationFiled: June 11, 2020Publication date: September 24, 2020Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SASInventors: Jean-Jacques FAGOT, Philippe BOIVIN, Franck ARNAUD
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Patent number: 10714501Abstract: An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.Type: GrantFiled: August 7, 2018Date of Patent: July 14, 2020Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SASInventors: Jean-Jacques Fagot, Philippe Boivin, Franck Arnaud
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Publication number: 20190371858Abstract: A MOS transistor with two vertical gates is formed within a substrate zone of a semiconductor substrate doped with a first type of conductivity and separated from a remaining portion of the substrate by two first parallel trenches extending in a first direction. An isolated gate region rests on each flank of the substrate zone and on a portion of the bottom of the corresponding trench to form the two vertical gates. At least one gate connection region electrically connects the two vertical gates. A first buried region located under the substrate zone is doped with a second type of conductivity to form a first conduction electrode of the MOS transistor. A second region doped with the second type of conductivity is located at the surface of the substrate zone to form a second conduction electrode of the MOS transistor.Type: ApplicationFiled: August 16, 2019Publication date: December 5, 2019Applicant: STMicroelectronics (Rousset) SASInventors: Philippe BOIVIN, Jean-Jacques FAGOT
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Publication number: 20190312088Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.Type: ApplicationFiled: April 4, 2019Publication date: October 10, 2019Inventors: Philippe BOIVIN, Jean Jacques FAGOT, Emmanuel PETITPREZ, Emeline SOUCHIER, Olivier WEBER
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Patent number: 10431630Abstract: A MOS transistor with two vertical gates is formed within a substrate zone of a semiconductor substrate doped with a first type of conductivity and separated from a remaining portion of the substrate by two first parallel trenches extending in a first direction. An isolated gate region rests on each flank of the substrate zone and on a portion of the bottom of the corresponding trench to form the two vertical gates. At least one gate connection region electrically connects the two vertical gates. A first buried region located under the substrate zone is doped with a second type of conductivity to form a first conduction electrode of the MOS transistor. A second region doped with the second type of conductivity is located at the surface of the substrate zone to form a second conduction electrode of the MOS transistor.Type: GrantFiled: February 20, 2017Date of Patent: October 1, 2019Assignee: STMicroelectronics (Rousset) SASInventors: Philippe Boivin, Jean-Jacques Fagot
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Publication number: 20190057981Abstract: An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.Type: ApplicationFiled: August 7, 2018Publication date: February 21, 2019Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SASInventors: Jean-Jacques FAGOT, Philippe BOIVIN, Franck ARNAUD
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Publication number: 20180076265Abstract: A MOS transistor with two vertical gates is formed within a substrate zone of a semiconductor substrate doped with a first type of conductivity and separated from a remaining portion of the substrate by two first parallel trenches extending in a first direction. An isolated gate region rests on each flank of the substrate zone and on a portion of the bottom of the corresponding trench to form the two vertical gates. At least one gate connection region electrically connects the two vertical gates. A first buried region located under the substrate zone is doped with a second type of conductivity to form a first conduction electrode of the MOS transistor. A second region doped with the second type of conductivity is located at the surface of the substrate zone to form a second conduction electrode of the MOS transistor.Type: ApplicationFiled: February 20, 2017Publication date: March 15, 2018Applicant: STMicroelectronics (Rousset) SASInventors: Philippe Boivin, Jean-Jacques Fagot