Patents by Inventor Jean-Jacques Hajjar

Jean-Jacques Hajjar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10581423
    Abstract: Fault tolerant switches are provided herein. In certain embodiments, a fault tolerant switch includes a switch, a gate driver, and a clamp. The switch includes a switch p-type field effect transistor (PFET) and a switch n-type field effect transistor (NFET) electrically connected in series and controlled by the gate driver. Additionally, the clamp is electrically connected in parallel with the switch, and includes a forward protection circuit including a first diode and a first clamp FET in series, and a reverse protection circuit including a second diode and a second clamp FET in series. The clamp further includes a first gate bias circuit configured to bias a gate of the first clamp FET and a second gate bias circuit configured to bias a gate of the second clamp FET.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: March 3, 2020
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Srivatsan Parthasarathy, Sirui Luo, Thomas Paul Kearney, Yuanzhong Zhou, Donal Bourke, Jean-Jacques Hajjar
  • Publication number: 20200059228
    Abstract: Fault tolerant switches are provided herein. In certain embodiments, a fault tolerant switch includes a switch, a gate driver, and a clamp. The switch includes a switch p-type field effect transistor (PFET) and a switch n-type field effect transistor (NFET) electrically connected in series and controlled by the gate driver. Additionally, the clamp is electrically connected in parallel with the switch, and includes a forward protection circuit including a first diode and a first clamp FET in series, and a reverse protection circuit including a second diode and a second clamp FET in series. The clamp further includes a first gate bias circuit configured to bias a gate of the first clamp FET and a second gate bias circuit configured to bias a gate of the second clamp FET.
    Type: Application
    Filed: January 2, 2019
    Publication date: February 20, 2020
    Inventors: Srivatsan Parthasarathy, Sirui Luo, Thomas Paul Kearney, Yuanzhong Zhou, Donal Bourke, Jean-Jacques Hajjar
  • Patent number: 7868387
    Abstract: A high-voltage, low-leakage, bidirectional electrostatic discharge (ESD, or other electrical overstress) protection device includes a doped well disposed between the terminal regions and the substrate. The device includes an embedded diode for conducting current in one direction, and a transistor feedback circuit for conducting current in the other direction. Variations in the dimensions and doping of the doped well, as well as external passive reference via resistor connections, allow the circuit designer to flexibly adjust the operating characteristics of the device, such as trigger voltage and turn-on speed, to suit the required mixed-signal operating conditions.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: January 11, 2011
    Assignee: Analog Devices, Inc.
    Inventors: Javier A. Salcedo, Jean-Jacques Hajjar, Todd Thomas
  • Publication number: 20090309128
    Abstract: A high-voltage, low-leakage, bidirectional electrostatic discharge (ESD, or other electrical overstress) protection device includes a doped well disposed between the terminal regions and the substrate. The device includes an embedded diode for conducting current in one direction, and a transistor feedback circuit for conducting current in the other direction. Variations in the dimensions and doping of the doped well, as well as external passive reference via resistor connections, allow the circuit designer to flexibly adjust the operating characteristics of the device, such as trigger voltage and turn-on speed, to suit the required mixed-signal operating conditions.
    Type: Application
    Filed: June 13, 2008
    Publication date: December 17, 2009
    Applicant: ANALOG DEVICES, INC.
    Inventors: Javier A. Salcedo, Jean-Jacques Hajjar, Todd Thomas