Abstract: This communication network (18) extends between a plurality of input blocks (E1, . . . , EN1) comprising a predetermined number P1 of input ports and a plurality of output blocks (S1, . . . , SN2) comprising at least the same number P2 of output ports as the predetermined number P1. In this network, when the result of the multiplication of the number of input ports P1 by the number of input blocks N1 is even, the number N3 of switches is equal to: N ? ? 3 = N ? ? 1 × P ? ? 1 2 , and when the result of said multiplication is odd, the number N3 of switches is equal to: N ? ? 3 = N ? ? 1 × P ? ? 1 - 1 2 , and, for each switch, the first (30) and second (32) input terminals are each connected to different input blocks (E1, . . . , EN1) and the first (34) and second (36) output terminals are each connected to different output blocks (S1, . . . , SN2).

Abstract: This communication network (18) extends between a plurality of input blocks (E1, . . . , EN1) including a predetermined number P1 of input ports, multiple of the number N1 of input blocks, and a plurality of output blocks (S1, . . . , SN2), each output block including a number P2 of output ports (Z1, . . . , ZP2) greater than or equal to the predetermined number of input ports. In this network, when the number P1 of input ports is even, the number N3 of switches is equal to: N ? ? 3 = N ? ? 1 × P ? ? 1 2 , and when the number P1 is odd, the number N3 of switches is equal to: N ? ? 3 = N ? ? 1 P ? ? 1 × P ? ? 1 2 - 1 2 , and, for each switch, the first (30) and second (32) input terminals are each connected to different input blocks and the first (34) and second (36) output terminals are each connected to different output blocks.

Abstract: This communication network (18) extends between a plurality of input blocks (E1, . . . , EN1) including a predetermined number P1 of input ports, multiple of the number N1 of input blocks, and a plurality of output blocks (S1, . . . , SN2), each output block including a number P2 of output ports (Z1, . . . , ZP2) greater than or equal to the predetermined number of input ports. In this network, when the number P1 of input ports is even, the number N3 of switches is equal to: N ? ? 3 = N ? ? 1 × P ? ? 1 2 , and when the number P1 is odd, the number N3 of switches is equal to: N ? ? 3 = N ? ? 1 P ? ? 1 × P ? ? 1 2 - 1 2 , and, for each switch, the first (30) and second (32) input terminals are each connected to different input blocks and the first (34) and second (36) output terminals are each connected to different output blocks.

Abstract: This communication network (18) extends between a plurality of input blocks (E1, . . . , EN1) including a predetermined number P1 of input ports and a plurality of output blocks (S1, . . . , SN2) including at least the same number P2 of output ports as the predetermined number P1. In this network, when the result of the multiplication of the number of input ports P1 by the number of input blocks N1 is even, the number N3 of switches is equal to: N ? ? 3 = N ? ? 1 × P ? ? 1 2 , and when the result of the multiplication is odd, the number N3 of switches is equal to: N ? ? 3 = N ? ? 1 × P ? ? 1 - 1 2 , and, for each switch, the first (30) and second (32) input terminals are each connected to different input blocks (E1, . . . , EN1) and the first (34) and second (36) output terminals are each connected to different output blocks (S1, . . . , SN2).

Abstract: The demodulator therefore features a multiplexer connected to the different transmission channels. The output of the multiplexer is connected to a sampler-coder, followed by an interpolator, which is itself followed by a phase jump converter and a statistical decision device validating the code conversion result, when a certain number of samples taken in a series of successive samples have a phase jump in the same range of values.

Abstract: The words to be added together by the high-speed sequential adder are stored in shift registers 1.sub.l to 1.sub.p whose serial outputs are connected to the corresponding inputs of a transcoder 2 producing the binary number of "1's" for each bit weight of the words to be added. This value is sent to an adder-divider 4 which adds it to the number of carried "1's" from the immediately lesser weight and divides this sum by 2, sending the fractional part of this half-sum to an output register 5 and the whole-number part to a carry register.Application: digital filters for PCM telephone switching.

Abstract: A digital filter for shared-time processing on several channels. The filter has several elementary cells (C.sub.1 to C.sub.K), each comprising a read-write memory (M.sub.1 to M.sub.K), a read-only memory (H.sub.1 to H.sub.K), and an arithmetic unit (U.sub.1 to U.sub.K). A page address counter CT.sub.1, a word address counter CT.sub.2 and a weighting coefficient address counter CT.sub.3 are common to the cells. Delayed discrete values are transferred by the relative addressing of the memory words. The filter will find particular application as a half-band extrapolator filter for telephone switching.