Abstract: A testing circuit configures an analog to digital converter (ADC) to receive a test signal instead of a live input signal. The testing circuit compares an output test value from the ADC to an expected test value for the test signal. The testing circuit provides an expected live output value to a digital circuit instead of the output test value, thereby preventing the ADC from providing a value to the digital circuit not based on the live input signal.

Abstract: A technique that minimizes false triggering of an electrostatic discharge (ESD) protection circuit is disclosed. In an embodiment, the resistor-capacitor (RC) time constant of an ESD trigger element is reduced during normal operation minimizing the risk of false triggering. Circuit layout area is saved without the need of a timeout circuit associated with releasing a device maintaining a trigger state (i.e., a trigger latch). A RC time constant for triggering is set in an operational context according to conditions of usage and desired application of the ESD protection circuit.

Abstract: A technique that minimizes false triggering of an electrostatic discharge (ESD) protection circuit is disclosed. In an embodiment, the resistor-capacitor (RC) time constant of an ESD trigger element is reduced during normal operation minimizing the risk of false triggering. Circuit layout area is saved without the need of a timeout circuit associated with releasing a device maintaining a trigger state (i.e., a trigger latch). A RC time constant for triggering is set in an operational context according to conditions of usage and desired application of the ESD protection circuit.

Abstract: A current cell for switch current circuits includes first and second MOS transistors connected in series between a constant current source and a reference ground. The first MOS transistor has its drain coupled to the constant current source and the second MOS transistor has its source coupled to the reference ground. Each of the two MOS transistors has a respective first and second switch coupling its control gate to its drain. The sample phase of a sample and hold operation is broken down into a first and second sample sub-phase, and an input current is applied to the current cell during both sample sub-phases. During the first sample sub-phase, the second MOS transistor memorizes a gate voltage corresponding to the input current, constant current source current and a clock feedthrough error. A channel effect is purposely induced in the second MOS transistor to a degree sufficient to compensate for, and correct, its clock feedthrough error.