Patents by Inventor Jean Jalade
Jean Jalade has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7109609Abstract: The invention concerns the control of thyristor-type semiconductor power components (Sw) powered by an alternating current network (VS). The control signal is a pulse (Ie). It is stored in the form of magnetic induction (B), positive or negative, in a core (T) made of ferromagnetic material. At each current alternation of the network, the interrogation of the magnetic state of the strand results in the presence, or not, of a control signal on the power device (Sw).Type: GrantFiled: October 30, 2001Date of Patent: September 19, 2006Assignee: STMicroelectronics S.A.Inventors: Jean Jalade, Jean-Pierre Laur, Jean-Louis Sanchez, Patrick Austin, Marie Breil, Eric Bernier
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Patent number: 6831328Abstract: The invention concerns an anode voltage sensor of a vertical power component selected from the group consisting of components called thyristor, MOS, IGBT, PMCT, EST, BRT transistor, MOS thyristor, turn-off MOS thyristor, formed by a lightly doped N-type substrate (1) whereof the rear surface (2) having a metallizing coat corresponds to the component anode. Said sensor comprises, on the front surface side, a substrate zone (12) surrounded at least partly by a P-type region with low potential in front of an anode potential, said zone (12) being coated with a metallizing coat (M) in ohmic contact with it, whereon is provided an image of the anode voltage.Type: GrantFiled: May 16, 2003Date of Patent: December 14, 2004Assignee: Centre National de la Recherche ScientifiqueInventors: Patrick Austin, Jean-Pierre Laur, Olivier Causse, Marie Breil, Jean-Louis Sanchez, Jean Jalade
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Patent number: 6703681Abstract: The invention concerns a variable capacitance capacitor comprising a periodic structure of raised zones (5) separated by recesses (6) formed in a type N semiconductor substrate (1). The walls of the raised zones and the base of the recesses are coated with a conductive layer (9, 10). The substrate is connected to a first terminal (A) of the capacitor and the conductive layer to a second terminal (B) of the capacitor. At least the base of the recesses or the side of the raised zones comprises type P regions (8), the pitch of the raised parts being selected so that the space charging zones linked to the type P regions are joined when the voltage difference between said terminals exceeds a predetermined threshold. The zones not comprising type P regions are coated with an insulant (7) and a highly doped N region (10) is formed beneath the insulant.Type: GrantFiled: May 16, 2003Date of Patent: March 9, 2004Assignee: Centre National de la Recherche ScientifiqueInventors: Jean-Louis Sanchez, Jean-Pierre Laur, Hedi Hakim, Patrick Austin, Jean Jalade, Marie Breil
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Publication number: 20040027005Abstract: The invention concerns the control of thyristor-type semiconductor power components (Sw) powered by an alternating current network (VS). The control signal is a pulse (Ie). It is stored in the form of magnetic induction (B), positive or negative, in a core (T) made of ferromagnetic material. At each current alternation of the network, the interrogation of the magnetic state of the strand results in the presence, or not, of a control signal on the power device (Sw).Type: ApplicationFiled: April 29, 2003Publication date: February 12, 2004Inventors: Jean Jalade, Jean-Pierre Laur, Jean-Louis Sanchez, Patrick Austin, Marie Breil, Eric Bernier
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Publication number: 20030183866Abstract: The invention concerns a variable capacitance capacitor comprising a periodic structure of raised zones (5) separated by recesses (6) formed in a type N semiconductor substrate (1). The walls of the raised zones and the base of the recesses are coated with a conductive layer (9, 10). The substrate is connected to a first terminal (A) of the capacitor and the conductive layer to a second terminal (B) of the capacitor. At least the base of the recesses or the side of the raised zones comprises type P regions (8), the pitch of the raised parts being selected so that the space charging zones linked to the type P regions are joined when the voltage difference between said terminals exceeds a predetermined threshold. The zones not comprising type P regions are coated with an insulant (7) and a highly doped N region (10) is formed beneath the insulant.Type: ApplicationFiled: May 16, 2003Publication date: October 2, 2003Inventors: Jean-Louis Sanchez, Jean-Pierre Laur, Hedi Hakim, Patrick Austin, Jean Jalade, Marie Breil
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Publication number: 20030174008Abstract: The invention concerns an anode voltage sensor of a vertical power component selected from the group consisting of components called thyristor, MOS, IGBT, PMCT, EST, BRT transistor, MOS thyristor, turn-off MOS thyristor, formed by a lightly doped N-type substrate (1) whereof the rear surface (2) having a metallizing coat corresponds to the component anode. Said sensor comprises, on the front surface side, a substrate zone (12) surrounded at least partly by a P-type region with low potential in front of an anode potential, said zone (12) being coated with a metallizing coat (M) in ohmic contact with it, whereon is provided an image of the anode voltage.Type: ApplicationFiled: May 16, 2003Publication date: September 18, 2003Inventors: Patrick Austin, Jean-Pierre Laur, Olivier Causse, Marie Breil, Jean-Louis Sanchez, Jean Jalade
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Patent number: 6542022Abstract: An analog voltage pulse generator, including a first break-over component of Shockley diode type to activate a rising edge of a pulse on an output terminal and a second component of thyristor type to block the first component and deactivate the pulse.Type: GrantFiled: December 20, 2000Date of Patent: April 1, 2003Assignee: STMicroelectronics S.A.Inventors: Laurent Gonthier, Mickael Destouches, Jean Jalade
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Patent number: 6459102Abstract: A peripheral structure for a monolithic power device, preferably planar, includes front and rear surfaces, connected respectively to a cathode and an anode, two junctions respectively reverse-biased and forward-biased when a direct and adjacent voltage is respectively applied to the two surfaces and at least an insulating box connecting the front and rear surfaces. The structure is such that when a direct voltage or a reverse voltage is applied, generating equipotential voltage lines, the insulating box enables to distribute the equipotential lines in the substrate.Type: GrantFiled: October 9, 2001Date of Patent: October 1, 2002Assignee: Centre National de la Recherche ScientifiqueInventors: Patrick Austin, Jean-Louis Sanchez, Olivier Causse, Marie Breil, Jean-Pierre Laur, Jean Jalade
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Patent number: 6326648Abstract: A monolithic power switch with a controlled di/dt including the parallel assembly of a MOS or IGBT type component with a thyristor type component, including means for inhibiting the thyristor type component during the closing phase of the switch, which is ensured by the IGBT type component. The IGBT type component has a vertical multicell structure and the component of thyristor type has a vertical monocell structure.Type: GrantFiled: December 20, 1999Date of Patent: December 4, 2001Assignee: STMicroelectronics S.A.Inventors: Jean Jalade, Jean-Louis Sanchez, Jean-Pierre Laur, Marie Breil, Patrick Austin, Eric Bernier, Mathieu Roy
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Publication number: 20010043111Abstract: An analog voltage pulse generator, including a first break-over component of Shockley diode type to activate a rising edge of a pulse on an output terminal and a second component of thyristor type to block the first component and deactivate the pulse.Type: ApplicationFiled: December 20, 2000Publication date: November 22, 2001Inventors: Laurent Gonthier, Mickael Destouches, Jean Jalade
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Patent number: 6188267Abstract: The present invention relates to a component forming a normally on dual thyristor, which can be turned off by a voltage pulse on the control electrode, including a thyristor, a first depletion MOS transistor, the gate of which is connected to the source, connected between the anode gate and the cathode of the thyristor, and a second enhancement MOS transistor, the gate of which is connected to a control terminal.Type: GrantFiled: April 15, 1999Date of Patent: February 13, 2001Assignee: Centre National de la Recherche ScientifiqueInventors: Jean-Louis Sanchez, Jean Jalade, Jean-Pierre Laur, Henri Foch
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Patent number: 6107664Abstract: A static self-locking micro-circuit-breaker includes a first MOS depletion transistor of a first type connected by its drain to a first main terminal and by its gate to a second main terminal, a second MOS depletion transistor of second type connected by its drain to the second main terminal and by its source to the source of the first transistor, a third MOS depletion transistor of the first type connected by its drain to the first main terminal, by its gate to the second main terminal, and by its source to the gate of the second transistor.Type: GrantFiled: July 14, 1997Date of Patent: August 22, 2000Assignee: SGS-Thomson Microelectronics S.A.Inventors: Jean-Baptiste Quoirin, Jean Jalade, Jean-Louis Sanchez, Jean-Pierre Laur
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Patent number: 5956582Abstract: A two-terminal current limiting component, includes a substrate of a first conductivity type; separated wells of the second conductivity type; a first annular region of the first conductivity type in each well; a second annular region of the first conductivity type having a low doping level between the periphery of each first annular region and the periphery of each well; an insulating layer over the second annular region and the surface portions of the substrate; a first metallization coating the upper surface of the component; and a second metallization coating the lower surface of the component.Type: GrantFiled: June 13, 1997Date of Patent: September 21, 1999Assignee: SGS-Thomson Microelectronics S.A.Inventors: Christophe Ayela, Philippe Leturcq, Jean Jalade, Jean-Louis Sanchez