Abstract: Various methods and semiconductor structures for fabricating at least one FET device having textured gate-source-drain contacts of the FET device that reduce or eliminate variability in parasitic resistance between the contacts of the FET device. An example fabrication method includes epitaxially growing a source-drain contact region on an underlying semiconductor substrate of one of a pFET device or an nFET device. The method deposits a bottom film layer directly on the epitaxially grown source-drain contact region. A first anneal forms a textured bottom silicide film layer directly on the epitaxially grown source-drain contact region. A top metal film layer is deposited on the textured bottom silicide film layer. A second anneal forms a textured top metal silicide film layer. The method can be repeated on the other one of the pFET device or the nFET device.

Abstract: Various methods and semiconductor structures for fabricating at least one FET device having textured gate-source-drain contacts of the FET device that reduce or eliminate variability in parasitic resistance between the contacts of the FET device. An example fabrication method includes epitaxially growing a source-drain contact region on an underlying semiconductor substrate of one of a pFET device or an nFET device. The method deposits a bottom film layer directly on the epitaxially grown source-drain contact region. A first anneal forms a textured bottom silicide film layer directly on the epitaxially grown source-drain contact region. A top metal film layer is deposited on the textured bottom silicide film layer. A second anneal forms a textured top metal silicide film layer. The method can be repeated on the other one of the pFET device or the nFET device.

Abstract: Various methods and semiconductor structures for fabricating at least one FET device having textured gate-source-drain contacts of the FET device that reduce or eliminate variability in parasitic resistance between the contacts of the FET device. An example fabrication method includes epitaxially growing a source-drain contact region on an underlying semiconductor substrate of one of a pFET device or an nFET device. The method deposits a Nickel film layer directly on the epitaxially grown source-drain contact region. A first anneal forms a textured Nickel silicide film layer directly on the epitaxially grown source-drain contact region. A second metal film layer is deposited on the textured Nickel silicide film layer. A second anneal forms a textured second metal silicide film layer. The method can be repeated on the other one of the pFET device or the nFET device.