Abstract: A charge pump circuit for use with a phase locked loop is described. The circuit has an input port for receiving a signal indicative of a misalignment between two clock signals. It also has an output port at which a drive signal is provided. The drive signal is provided when the comparison result is indicative of misalignment of the signals. When the signals are aligned, a high impedance is provided at the output port and the charge pump circuit or a portion thereof enter a sleep mode to reduce power consumption of the charge pump when providing a high impedance at the output port.

Abstract: An asynchronous counter includes a plurality of flip-flops, cascade connected to one another, the plurality of flip-flops serially receiving successive pulse trains having varying numbers of pulses per pulse train. Switching circuitry, coupled to the plurality of flip-flops, inverts the state of each flip-flop between a first set of pulse trains and a second set of pulse trains (or first and second consecutive pulse trains) so that the counter computes a difference between the number of pulses in the first set of pulse trains and the number of pulses in the second set of pulse trains (or a difference between the number of pulses of the first pulse train and the number of the second pulse train). Initialization circuitry, coupled to the plurality of flip-flops, initializes all of the flip-flops at each predetermined even number of pulse trains.