Patents by Inventor Jean Louis Calvignac
Jean Louis Calvignac has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20030009453Abstract: A method and system for performing a pattern match search for a data string having a plurality of characters separated by delimiters. In accordance with the method of the present invention a search key is constructed by generating a full match search increment comprising the binary representation of a data string element, wherein the data string element comprises all characters between a pair of delimiters. The search key is completed by concatenating a pattern search prefix to the full match search increment, wherein the pattern search prefix is a cumulative pattern search result of each previous full match search increment. A full match search is then performed within a lookup table utilizing the search key. In response to finding a matching pattern within the lookup table, the process returns to constructing a next search key. In response to not finding a matching pattern, the previous full match search result is utilized to process the data string.Type: ApplicationFiled: July 3, 2001Publication date: January 9, 2003Applicant: International Business Machines CorporationInventors: Claude Basso, Jean Louis Calvignac, Philippe Damon, Gordon Taylor Davis, Marco C. Heddes, Clark Debs Jeffries
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Publication number: 20030002440Abstract: An ordered semaphore management subsystem and method for use in an application system which includes a plurality of processors competing for shared resources each of which is controlled by a unique semaphore. The subsystem generates an ordered semaphore field (OSF) corresponding to each processor in a linked list of processors and assigns one of four statuses to the OSF depending on the position the processor occupies in the linked list of processors competing for the shared resources. The four states are (1) semaphore head (SH); (2) behind semaphore head (BSH); (3) semaphore head behind (SHB); and (4) skip (Skip). Only the SH processor is allocated the semaphore when requested. A processor not in the SH state will be denied the semaphore even if is available to assure sequential access.Type: ApplicationFiled: June 25, 2002Publication date: January 2, 2003Applicant: International Business Machines CorporationInventors: Jean Louis Calvignac, Gordon Taylor Davis, Marco Heddes, Steven Kenneth Jenkins, Ross Boyd Leavens, Robert Brian Likovich
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Patent number: 6498781Abstract: A data processing system and method in a computer network are disclosed for improving performance of a link aggregation system included in the network. Parameters are established which are utilized to determine performance criteria of the link aggregation system. A performance of the link aggregation system is determined by determining the performance criteria. The performance of the link aggregation system changes in response to a flow traffic burden on the link aggregation system changing. The link aggregation system dynamically modifies the parameters in response to the changing performance of the link aggregation system. The link aggregation system is self-tuning and capable of automatically adjusting to a changing flow traffic burden on the link aggregation system.Type: GrantFiled: August 13, 1999Date of Patent: December 24, 2002Assignee: International Business Machines CorporationInventors: Brian Mitchell Bass, Jean Louis Calvignac, Marco C. Heddes, Clark Debs Jeffries, Loren Douglas Larsen, Jeffrey James Lynch, Mark Anthony Rinaldi, Michael Steven Siegel
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Publication number: 20020191642Abstract: An interface to interconnect chips in a multi-chip system includes a limited set of messages and circuit arrangements to generate the limited set of messages. The chips can be configured in different operational modes which dictates what portion of a frame is to be transmitted between selected chips of the system.Type: ApplicationFiled: March 12, 2002Publication date: December 19, 2002Applicant: International Business Machines CorporationInventors: Jean Louis Calvignac, Marco Heddes, Joseph Franklin Logan
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Publication number: 20020176429Abstract: An interface to interconnect Network Processor and Scheduler chips in a multi-chip system includes a limited set of messages and circuit arrangements to generate the limited set of messages. The messages include FlowEnqueue.request, FlowEnqueue.response, PortEnqueue.request and PortStatus.request.Type: ApplicationFiled: March 12, 2002Publication date: November 28, 2002Applicant: International Business Machines CorporationInventors: Jean Louis Calvignac, Marco Heddes, Joseph Franklin Logan
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Patent number: 6473838Abstract: The ability of network processors to move data to and from dynamic random access memory (DRAM) chips used in computer systems is enhanced in several respects. In one aspect of the invention, two double data rate DRAMS are used in parallel to double the bandwidth for increased throughput of data. The movement of data is further improved by setting 4 banks of full ‘read’ and 4 banks of full ‘write’ by the network processor for every repetition of the DRAM time clock. A scheme for randomized ‘read’ and ‘write’ access by the network processor is disclosed. This scheme is particularly applicable to networks such as Ethernet that utilize variable frame sizes.Type: GrantFiled: January 4, 2000Date of Patent: October 29, 2002Assignee: International Business Machines CorporationInventors: Brian Mitchell Bass, Jean Louis Calvignac, Marco C. Heddes, Steven Kenneth Jenkins, Michael Steven Siegel, Michael Raymond Trombley, Fabrice Jean Verplanken
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Publication number: 20020154634Abstract: Data structures, a method, and an associated transmission system for multicast transmission on network processors in order both to minimize multicast transmission memory requirements and to account for port performance discrepancies. Frame data for multicast transmission on a network processor is read into buffers to which are associated various control structures and a reference frame. The reference frame and the associated control structures permit multicast targets to be serviced without creating multiple copies of the frame. Furthermore this same reference frame and control structures allow buffers allocated for each multicast target to be returned to the free buffer queue without waiting until all multicast transmissions are complete.Type: ApplicationFiled: April 20, 2001Publication date: October 24, 2002Applicant: International Business Machines CorporationInventors: Claude Basso, Jean Louis Calvignac, Marco C. Heddes, Joseph Franklin Logan, Fabrice Jean Verplanken
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Publication number: 20020156908Abstract: Data structures, a method, and an associated transmission system for IP fragmentation and IP reassembly on network processors in order to minimize memory allocation requirements. Frame data for IP fragmentation or reassembly on a network processor is read into buffers to which are associated various control structures. The control structures permit IP fragmentation or reassembly to be accomplished without creating multiple copies of the frame or fragments.Type: ApplicationFiled: April 20, 2001Publication date: October 24, 2002Applicant: International Business Machines CorporationInventors: Claude Basso, Jean Louis Calvignac, Marco C. Heddes, Joseph Franklin Logan, Fabrice Jean Verplanken
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Publication number: 20020149989Abstract: Network processors commonly utilize DRAM chips for the storage of data. Each DRAM chip contains multiple banks for quick storage of data and access to that data. Latency in the transfer or the ‘write’ of data into memory can occur because of a phenomenon referred to as memory bank polarization. By a procedure called quadword rotation, this latency effect is effectively eliminated. Data frames received by the network processor are transferred to a receive queue (FIFO). The frames are divided into segments that are written into the memory of the DRAM in accordance with a formula that rotates the distribution of each segment into the memory banks of the DRAM.Type: ApplicationFiled: February 23, 2001Publication date: October 17, 2002Applicant: International Business Machines CorporationInventors: Jean Louis Calvignac, Peter Irma August Barri, Ivan Oscar Clemminck, Kent Harold Haselhorst, Marco C. Heddes, Joseph Franklin Logan, Bart Joseph Gerard Pauwels, Fabrice Jean Verplanken, Miroslav Vrana
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Publication number: 20020147830Abstract: A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes a plurality of control blocks, one for each data buffer, each containing control information to link one buffer to another for transmission. Each of the control blocks has a last bit feature which is a single bit and indicates when the data buffer having the last bit is transmitted. This last bit feature is a bit which can be set to either zero or one. The last bit feature is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer.Type: ApplicationFiled: April 6, 2001Publication date: October 10, 2002Applicant: International Business Machines CorporationInventors: Claude Basso, Jean Louis Calvignac, Marco C. Heddes, Joseph Franklin Logan, Fabrice Jean Verplanken
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Patent number: 6460120Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a plurality of memory elements and a plurality of interface processors formed on a semiconductor substrate. The memory elements and interface processors together form a network processor capable of cooperating with other elements in executing instructions directing the flow of data in a network. Access to the memory elements is controlled in a particular manner and under operative rules which provide controlled multiple accesses of the plurality of memory elements by the plurality of processors.Type: GrantFiled: August 27, 1999Date of Patent: October 1, 2002Assignee: International Business Machines CorporationInventors: Brian Mitchell Bass, Jean Louis Calvignac, Marco C. Heddes, Piyush Chunilal Patel, Juan Guillermo Revilla, Michael Steven Siegel, Fabrice Jean Verplanken
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Publication number: 20020130797Abstract: A 2-bit communication channel is made to transmit complex data patterns by partitioning a digital string into 3-bit binary patterns which are encoded into 4 bits binary pattern and transmitted over the 2-bit communication channel in pairs using adjacent clock cycles on the 2-bit channel. Pre-defined ones of the 4-bit encoded data structures are used for framing on the channel and cannot be used to transmit data.Type: ApplicationFiled: March 12, 2002Publication date: September 19, 2002Applicant: International Business Machines CorporationInventors: Jean Louis Calvignac, Jeffrey James Lynch, Daniel James Sucher, Fabrice Jean Verplanken
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Patent number: 6449576Abstract: A method and system for systematically accessing and monitoring operating parameter signals within an IC device. A probe configuration logic selects a subset of signals from among a set of available signals within a physical or logical subdivision of the IC device. Signal access logic selectively provides physical or logical access from the selected subset of signals within the physical or logical subdivision of the IC device to a probe sensor, such that IC device operations may be flexibly and comprehensively monitored. A local mode selector provides remote access to the selected subset of signals at an input/output (I/O) data interface. Data packaging logic in communication with the probe sensor permits port mirroring of the I/O data interface.Type: GrantFiled: March 29, 2000Date of Patent: September 10, 2002Assignee: International Business Machines CorporationInventors: Brian Mitchell Bass, Jean Louis Calvignac, Anthony Matteo Gallo, Marco C. Heddes, Michael Steven Siegel, Fabrice Jean Verplanken, Chad Everett Winemiller
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Publication number: 20020122386Abstract: A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure.Type: ApplicationFiled: April 19, 2001Publication date: September 5, 2002Applicant: International Business Machines CorporationInventors: Jean Louis Calvignac, William John Goetzinger, Glen Howard Handlogten, Marco C. Heddes, Joseph Franklin Logan, James Francis Mikos, David Alan Norgaard, Fabrice Jean Verplanken
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Publication number: 20020118693Abstract: A method and system for reserving frame modification information in a data storage unit. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. The processor may comprise a data flow unit configured to receive and transmit frames of data. The processor may further comprise a data storage unit coupled to the data flow unit where the data storage unit comprises a plurality of buffers. The plurality of buffers is configured to store frames of data. A first buffer may be accessed to store the ending frame data of a first frame. A first bank in the first buffer stores the end of the first frame. A second bank in a second buffer may be reserved for storing frame modification information where the second bank corresponds to the first bank in the first buffer that stores the end of the first frame.Type: ApplicationFiled: February 23, 2001Publication date: August 29, 2002Applicant: International Business Machines CorporationInventors: Jean Louis Calvignac, Marco C. Heddes, Joseph Franklin Logan, Fabrice Jean Verplanken
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Publication number: 20020118690Abstract: A method and system for reducing the number of accesses to memory to obtain the desired field information in frame control blocks. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. The processor may comprise a data flow unit configured to receive and transmit frames of data, where each frame of data may have an associated frame control block. Each frame control block comprises a first and a second control block. The processor may further comprise a first memory coupled to the data flow unit configured to store field information for the first control block. The processor may further comprise a scheduler coupled to the data flow unit where the scheduler is configured to schedule frames of data received by data flow unit. The scheduler may comprise a second memory configured to store field information for the second control block.Type: ApplicationFiled: February 23, 2001Publication date: August 29, 2002Applicant: International Business Machines CorporationInventors: Jean Louis Calvignac, Marco C. Heddes, Joseph Franklin Logan, Fabrice Jean Verplanken
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Publication number: 20020118694Abstract: A method and system for reducing memory accesses by inserting qualifiers in control blocks. In one embodiment, a system comprises a processor configured to process frames of data. The processor may comprise a plurality of buffers configured to store frames of data where each frame of data may be associated with a frame control block. Each frame control block associated with a frame of data may be associated with one or more buffer control blocks. Each control block, e.g., frame control block, buffer control block, may comprise one or more qualifier fields that comprise information unrelated to the current control block. Instead, qualifiers may comprise information related to an another control block. The last frame control block in a queue as well as the last buffer control block associated with a frame control block may comprise fields with no information thereby reducing memory accesses to access information in those fields.Type: ApplicationFiled: February 23, 2001Publication date: August 29, 2002Applicant: International Business Machines CorporationInventors: Jean Louis Calvignac, Marco C. Heddes, Joseph Franklin Logan, Fabrice Jean Verplanken
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Publication number: 20020120890Abstract: A method and system for efficiently implementing an error correction code scheme. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. Each frame of data may be associated with a frame control block. The processor comprises a first queue configured to store one or more frame control blocks associated with one or more frames of data. The processor further comprises a second queue configured to store one or more frame control blocks not associated with a frame of data. The one or more frame control blocks associated with one or more frames of data in the first queue comprise a bit for storing a parity bit. The one or more frame control blocks in the second queue comprise a plurality of bits for storing a code of an error correction code scheme.Type: ApplicationFiled: February 23, 2001Publication date: August 29, 2002Applicant: International Business Machines CorporationInventors: Jean Louis Calvignac, Marco C. Heddes, Joseph Franklin Logan, Fabrice Jean Verplanken
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Publication number: 20020101985Abstract: A hardware implementation of a crypto-function is realized using combinational logic performing computation iterations of the crypto-function on data in a single hardware cycle. Only combinational logic is used to implement the entire cryptographic algorithm, and registers are used only to store input or output from the combinational logic, leading to a very high speed implementation of the crypto-function.Type: ApplicationFiled: January 26, 2001Publication date: August 1, 2002Applicant: International Business Machines CorporationInventors: Jean Louis Calvignac, Mohammad Peyravian, Fabrice Jean Verplanken
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Publication number: 20020071321Abstract: A Network Processor includes a Fat Pipe Port and a memory sub-system that provides sufficient data to satisfy the Bandwidth requirements of the Fat Pipe Port. The memory subsystem includes a plurality of DDR DRAMs controlled so that data is extracted from one DDR DRAM or simultaneously from a plurality of the DDR DRAMs. By controlling the DDR DRAMs so that the outputs provide data serially or in parallel, the data Bandwidth is adjustable over a wide range. Similarly, data is written serially into one DDR DRAM or simultaneously into multiple DDR DRAMs. As a consequence buffers with data from the same frame are written into or read from different DDR DRAMs.Type: ApplicationFiled: November 21, 2001Publication date: June 13, 2002Applicant: International Business Machines CorporationInventors: Peter Irma August Barri, Jean Louis Calvignac, Kent Harold Haselhorst, Marco C. Heddes, Joseph Franklin Logan, Fabrice Jean Verplanken, Miroslav Vrana