Abstract: This invention describes a test tool based on a PC workstation. This test tool is used to validate any E1 framing telecommunication device. In order to comply with the CCITT G.706 recommendations, a device has to pass a series of test cases that are predetermined. Each test case contains test sequences according to the CCITT G.706 specifications. The purpose of this test tool is to generate a set of stimuli in the transmission mode, whereas in the reception mode, the value of the data returned by the tested device is analyzed and compared with the expected response. The data bytes are structured as for E1 multiframe format containing 16 frames of 32 timeslots, where each timeslot is a data byte. According to the G.706 recommendations, timeslot 0 is dedicated to the frame and multiframe alignment and to the CRC test.

Abstract: A method for initializing ISDN adapter cards installed within a workstation having a main processor and an ISDN primary adapter for connecting the ISDN adapter cards to an ISDN primary gateway. Each ISDN adapter card has circuits for handling at least one B-channel, and a first processor associated with memory storage. The ISDN primary adapter includes a second processor associated with a second memory storage. In response to the reception of a specific polling pattern transmitted to each adapter card by the primary adapter, a pattern is transmitted to the workstation processor for requesting the loading of the second memory storage with operational code transferred from the workstation to the ISDN adapter card.

Abstract: Memory and peripheral chip select apparatus for allowing the addressing of different memory and peripheral elements by a processor. The different memory and peripheral elements include first memory elements and first peripheral elements located in a first adapter pluggable into a base machine and second memory elements and second peripheral elements located into a second adapter pluggable into the base machine. The processor further addresses third memory elements and third peripheral elements located in the base machine. The first and second memory elements include code which has a determined type and a determined level of release.