Abstract: A protection circuit against the electrostatic discharges that could appear at the terminals of a circuit, wherein said protection circuit comprises a first transistor made in a well whose potential is a floating potential and enabling the value of the discharge voltage to be limited to a value equal to minus the value of the threshold voltage of said first transistor and a second transistor made in a well whose potential is a floating potential and enabling the value of the discharge voltage to be limited to a value equal to the value of the threshold voltage of said second transistor. The disclosure can be applied to MOS technology integrated circuits.

Abstract: A method of detecting electromagnetic radiation imparted onto a matrix of photosensitive photomos networks in which pixels of each photomos network are simultaneously exposed to electromagnetic radiation source for a predetermined period of time. Thereafter, transfer signals are applied to each photomos pixel and accumulated charges corresponding to the strength of the radiation imparted onto the pixels are transferred in a columnwise fashion to the end of each column of the photomos networks. The charges are summed at the end of the columns and placed in a reading register. The charges in the reading register of each photomos network are summed and a signal is output corresponding to the strength of the electromagnetic radiation imparted onto the photomos network.

Abstract: A method of detecting electromagnetic radiation imparted onto a matrix of photosensitive photomos networks in which pixels of each photomos network are simultaneously exposed to electromagnetic radiation source for a predetermined period of time. Thereafter, transfer signals are applied to each photomos pixel and accumulated charges corresponding to the strength of the radiation imparted onto the pixels are transferred in a columnwise fashion to the end of each column of the photomos networks. The charges are summed at the end of the columns and placed in a reading register. The charges in the reading register of each photomos network are summed and a signal is output corresponding to the strength of the electromagnetic radiation imparted onto the photomos network.

Abstract: A charge transfer device for a linear photosensor is disclosed. It is necessary to provide for anti-dazzle devices to prevent charges, generated in excessive quantity by the photosensor, from saturating the read shift register. To prevent excess charges from being introduced into the register during the transfer between a storage gate and the register, and to enable a juxtaposition, with a small pitch, of the read elements of each photodiode of the reading device, a structure is proposed with an input diode De, and on a first side of the diode, an input gate, a storage gate and the gate for transfer to the shift register; these three elements are standard ones; on the other side, three successive gates, the first one being adjacent to a charge removal region. The potential imposed on the first of these three gates is greater than the potential imposed on the input gate of the other side of the diode.

Abstract: An analog multiplexing device using charge transfer devices has as many charge transfer multiplexing registers R'i as there are input signals, at the frequency F.sub.e, to be multiplexed, all of these registers preferably having the same length, and a single output register, the first stage of which is connected by a connection to the respective stages with levels i of the registers R'i, i=1 to n, enabling the reading by image charges of the input charges. The transfer into the successive stages of the multiplexing registers is done at a frequency nF.sub.e just as the transfer of the image charges read by the read connection in the output register stages.

Abstract: A multilinear charge transfer array is provided formed by N lines of P photosensitie detectors. Each photosensitive detector is connected directly by a connection to a demultiplexing and reading system, the signals obtained at the output of the array being fed to a processing device external to the array.The demultiplexing system comprises a charge transfer shift register with N.times.P stages, the connections between each detector and the corresponding input of the register being provided so that the detectors of the same rank are connected to contiguous inputs.

Abstract: A non recursive analog integrator providing M integrations of a sampled analog signal Vn,m. The integrator comprises a series parallel demultiplexer with N outputs, N capacitors each with an electrode connected to a floating potential with respect to a reference potential, and a parallel series multiplexer with N inputs, the respective capacitors being connected in parallel between the outputs of the demultiplexer and the inputs of the multiplexer. Each capacitor performs, at each integration, the summation in form of charges of the sample of corresponding rank of the sampled analog signal Vn,m. So, at the end of the M integrations, an analog signal- ##EQU1## is obtained at the output of the multiplexer. Charge transfer devices serve as the series parallel demultiplexer and as the parallel series multiplexer.

Abstract: In this transverse charge transfer filter having N MOS capacitors arranged on the same semiconductor substrate and provided with electrodes, the electrode of every other MOS capacitor has its ends covered by the ends of the electrodes of two adjacent MOS capacitors, the N MOS capacitors being arranged in n rows and the charge transfer direction in two adjacent rows being opposite, which makes it possible to compensate for the effects of the displacements of the masks used for manufacturing the transverse charge transfer filters.

Abstract: This invention concerns an analog-to-digital correlator with programmable coefficients with values of +1, -1 or 0.This correlator comprises a charge-transfer shift register to receive samples of the analog input signal for correlation, and two programmable digital-output shift registers, followed by memories to establish coefficients with values of +1, -1 or 0. Depending on the signal available at the digital register outputs:reading of charges is blocked on the analog register, corresponding to establishment of coefficient 0;reading of charges occurs, reaching either the positive or the negative input of a differential amplifier, corresponding to the establishment of coefficient +1 or -1.

Abstract: The switched-capacitance amplifier comprises n capacitors C.sub.11 to C.sub.1n which are periodically switched in parallel and in series, the n parallel-switched capacitors being charged simultaneously by the same voltage V.sub.E. An amplified voltage n.times.V.sub.E is obtained between the end terminals A and B of the n series-switched capacitors. Periodic switching of the n capacitors in parallel and in series is performed by means of MOS transistors T.sub.11 to T.sub.1(2n-1) and T.sub.21 to T.sub.2(n-1) which operate in the switching mode. The n capacitors and the MOS transistors are integrated on the same semiconductor substrate.

Abstract: A device for reading a quantity of electric charges arriving at a point B. Two MOS transistors Q2 and Q3 are connected in series and with one terminal to point B. A capacitor C.sub.A is connected to a common point A of the two transistors. A transistor control circuit charges the capacitor C.sub.A from a low potential V.sub.DD. The capacitor C.sub.A and the transistors Q2 and Q3 maintain a constant potential at the point B at the time of charge inflow. This results is a variation of potential at the common point A in accordance with the incoming charges at B. Thus, the variations of potential at point A is a measure of the charges arriving at point B.

Abstract: A phase shift circuit made from integrable semi-conductor elements. It comprises: a sampling stage formed by two MOS type transistors operating in phase opposition, which supply, from the input signal (S.sub.e), a sampled signal S.sub.ECH ; a first MOS type transistor which forms the phase shift element, receives signal S.sub.ECH on its gate and delivers two signals (S.sub.1 and S.sub.2), which are opposite in phase, at its drain and source respectively; two capacitors, which receive signals S.sub.1 and S.sub.2 respectively, and are associated with polarizing means containing MOS type transistors, which enable the original D.C. components of signals S.sub.1 and S.sub.2 to be replaced by the same D.C. component (V.sub.P).

Abstract: A differential charge-transfer device for transversal filtering or delay line applications. It comprises: two charge-transfer channels which respectively receive the two signals, the difference between which is to be formed; an electrode common to both channels; means for sampling the signals in each channel, this sampling taking place at the same instants in both channels; a set of electrodes in each channel which, on the application of potentials of period T, propagate the samples to the common electrode with a relative delay equal to T/2 from one channel to the other. The signal representing the difference between the input signals is extracted at the common electrode.