Abstract: A device for filtering positive dejustification jitter of a digital bit stream includes a phase-locked loop for slaving the timing of a signal representative of the read timing of a buffer memory into which the dejustified digital bit stream is written to the timing of a signal representative of the write timing of the buffer memory. The device applies low-pass filtering and determines the actual justification rate of the digital bit stream and deduces therefrom the difference justification rate, i.e. the difference between the actual rate and a nominal justification rate of the digital bit stream. It systematically eliminates phase shifts due to positive dejustification from the signal representative of the buffer memory write timing, regenerates phase shifts of the signal in numbers corresponding to the nominal justification rate, and regenerates phase shifts of the signal in numbers corresponding to the difference justification rate and smooths the phase shifts.

Abstract: A fully digital phase-locked loop comprises a sampler (1), an analog-to-digital converter (2), two quadrature demodulators (3 and 4) and their associated filters (5 and 6), and a decision logic (7) effecting the correction of the sampling phase around the value of the free-running frequency (f.sub.e) by the addition or subtraction of machine cycles of a signal processor (9).

Abstract: A transmission path between two terminal stations for transmitting digital information signals at a predetermined rate in one direction via a forward path and in the other direction via a return path. The transmission path comprises regenerative repeaters. A system for tele-location of these repeaters comprises in one of the terminal stations a transmitter for transmitting tele-location commands to the repeaters via the forward path, carrier signals of the said rate being on-off modulated in this transmitter by an amplitude modulator in accordance with output signals of a command sequence generator, and further comprises in every repeater a loop circuit between forward and return paths having an associated control circuit which cooperates with a detector for detecting the presence of carrier signals in the return path and for receiving tele-location commands.

Abstract: A balancing amplifier comprising a pair of transistors arranged as a differential amplifier and a negative feedback network including a transistor voltage follower as a part of the load circuit of each transistor of the pair of transistors. Owing to the negative feedback network high level signals can be balanced. The amplifier provides output signals in phase opposition from a single-ended input signal.