Abstract: A method of automatically testing electronic components in parallel, identical pins (i; i+1) of said components interchanging test signals with at least one common test circuit (20; 20') which includes, firstly, timing generators (22a, 22b, 22c, 22d; 22'a, 22'b, 22'c, 22'd) controlled by a test programming memory (10) and, secondly, forcing circuits (24.sub.1, 24.sub.2 ; 24'.sub.1, 24'.sub.2) and comparator circuits (26.sub.1, 26.sub.2 ; 26'.sub.1, 26'.sub.2) controlled by said timing generators. In accordance with the invention, all the timing generators are assigned to said forcing circuits or to said comparator circuits in such manner as to produce synchronous test signals at said identical pins (i) of said electronic components. Applications include automatic testing of components in parallel.

Abstract: Apparatus for selectively testing, in parallel, identical pins of a plurality of electronic components is provided. The apparatus enables testing of selective pins of selective electronic components according to different timing schemes.

Abstract: Apparatus for selectively testing, in parallel, identical pins of a plurality of electronic components is provided. The apparatus enables selective pins of selective electronic components to be disabled during testing so that testing can continue in connection with the identical pins of the remainder of the plurality of electronic components.