Abstract: Embodiments described herein include a method for depositing a material layer on a substrate while controlling a bow of the substrate and a surface roughness of the material layer. A bias applied to the substrate while the material layer is deposited is adjusted to control the bow of the substrate. A bombardment process is performed on the material layer to improve the surface roughness of the material layer. The bias and bombardment process improve a uniformity of the material layer and reduce an occurrence of the material layer cracking due to the bow of the substrate.

Abstract: Provided are methods for pre-cleaning a substrate. A substrate having tungsten oxide (WOx) thereon is soaked in tungsten fluoride (WF6), which reduces the tungsten oxide (WOx) to tungsten (W). Subsequently, the substrate is treated with hydrogen, e.g., plasma treatment or thermal treatment, to reduce the amount of fluorine present so that fluorine does not invade the underlying insulating layer.

Abstract: The present invention relates to a method for regulating potency of pluripotent stem cells (PSCs) by modulating expression of podocalyxin-like protein 1 (PODXL) and applications thereof.

Abstract: The present invention generally relates to a method for generating induced oligodendrocyte-lineage cells (induced OLGs) and treatment using such cells. The induced OLGs are useful in cell therapy, in particular for demyelinating diseases.

Abstract: The present invention relates to a method for removing undifferentiated embryonic stem cells. In particular, the present invention relates to a method for removing undifferentiated embryonic stem cells by using cardiac glycosides (CGs). The present invention also relates to a method for preparing differentiated cells in which undifferentiated embryonic stem cells have been removed and a method for cell therapy by using such differentiated cells.

Abstract: Embodiments described herein include a method for depositing a material layer on a substrate while controlling a bow of the substrate and a surface roughness of the material layer. A bias applied to the substrate while the material layer is deposited is adjusted to control the bow of the substrate. A bombardment process is performed on the material layer to improve the surface roughness of the material layer. The bias and bombardment process improve a uniformity of the material layer and reduce an occurrence of the material layer cracking due to the bow of the substrate.

Abstract: A system and method for a semiconductor wafer carrier is disclosed. An embodiment comprises a semiconductor wafer carrier wherein conductive dopants are implanted into the carrier in order to amplify the coulombic forces between an electrostatic chuck and the carrier to compensate for reduced forces that result from thinner semiconductor wafers. Another embodiment forms conductive layers and vias within the carrier instead of implanting conductive dopants.

Abstract: The present invention generally relates to a method for preparing induced mesenchymal stem cells (iMSCs) and its applications. The iMSCs, like MSCs, can differentiate into multiple lineages, which may be beneficial for disease treatments. In addition, the present invention also provides a method for improving the MSC's functional characteristics such that the MSCs are more suitable for cell therapy or in vitro applications.

Abstract: A system and method for a semiconductor wafer carrier is disclosed. An embodiment comprises a semiconductor wafer carrier wherein conductive dopants are implanted into the carrier in order to amplify the coulombic forces between an electrostatic chuck and the carrier to compensate for reduced forces that result from thinner semiconductor wafers. Another embodiment forms conductive layers and vias within the carrier instead of implanting conductive dopants.

Abstract: A system and method for a semiconductor wafer carrier is disclosed. An embodiment comprises a semiconductor wafer carrier wherein conductive dopants are implanted into the carrier in order to amplify the coulombic forces between an electrostatic chuck and the carrier to compensate for reduced forces that result from thinner semiconductor wafers. Another embodiment forms conductive layers and vias within the carrier instead of implanting conductive dopants.

Abstract: The invention is directed, in part, to compositions comprising small molecule compounds to treat or prevent hearing loss. Compositions of the present invention also promote sensory hair cell regeneration. Particular compositions comprise ellipticine derivatives, and optionally one or more small molecules that increase Atoh1 expression or activity, and optionally one or more growth factors.

Abstract: A three-dimensional integrated circuit (3D-IC) which incorporates a glass interposer and a method for fabricating the three-dimensional integrated circuit (3D-IC) with the glass interposer are described herein. In one embodiment, the 3D-IC incorporates a glass interposer which has vias formed therein which are not filled with a conductor that allow for precision metal-to-metal interconnects (for example) between redistribution layers. In another embodiment, the 3D-IC incorporates a glass interposer which has vias and has a coefficient of thermal expansion (CTE) that is different than the CTE of silicon which is 3.2 ppm/° C.

Abstract: The invention is directed, in part, to compounds of structure (I) to treat or prevent hearing loss. Compounds of the present invention also promote sensory hair cell regeneration. Particular compositions comprise compounds of structure (I), and optionally one or more small molecules that increase the proliferation of supporting cells.

Abstract: A system and method for a semiconductor wafer carrier is disclosed. An embodiment comprises a semiconductor wafer carrier wherein conductive dopants are implanted into the carrier in order to amplify the coulombic forces between an electrostatic chuck and the carrier to compensate for reduced forces that result from thinner semiconductor wafers. Another embodiment forms conductive layers and vias within the carrier instead of implanting conductive dopants.

Abstract: The invention is directed, in part, to compositions comprising small molecule compounds to treat or prevent hearing loss. Compositions of the present invention also promote sensory hair cell regeneration. Particular compositions comprise ellipticine derivatives, and optionally one or more small molecules that increase Atoh1 expression or activity, and optionally one or more growth factors.

Abstract: A system and method for a semiconductor wafer carrier is disclosed. An embodiment comprises a semiconductor wafer carrier wherein conductive dopants are implanted into the carrier in order to amplify the coulombic forces between an electrostatic chuck and the carrier to compensate for reduced forces that result from thinner semiconductor wafers. Another embodiment forms conductive layers and vias within the carrier instead of implanting conductive dopants.

Abstract: An airport surface collision-avoidance system (ASCAS). An exemplary system includes sensors (e.g., radar) at light modules about an aircraft, with user interface devices located with airport ground personnel and in the cockpit of the aircraft. The system helps to avoid collisions on the airport surface, i.e., during taxiing clear of airport buildings, during taxiing close to airport buildings, during gate operations (push-back and standing), etc. The system includes components for communicating sensor information to ground service equipment (tug tractor, baggage cart, refueling truck, etc.). The system can determine possible collision for any part of the aircraft (wingtip, tail assembly, engine cowl, fuselage, door, etc).

Abstract: A three-dimensional integrated circuit (3D-IC) which incorporates a glass interposer and a method for fabricating the three-dimensional integrated circuit (3D-IC) with the glass interposer are described herein. In one embodiment, the 3D-IC incorporates a glass interposer which has vias formed therein which are not filled with a conductor that allow for precision metal-to-metal interconnects (for example) between redistribution layers. In another embodiment, the 3D-IC incorporates a glass interposer which has vias and has a coefficient of thermal expansion (CTE) that is different than the CTE of silicon which is 3.2 ppm/° C.

Abstract: A system and method for a semiconductor wafer carrier is disclosed. An embodiment comprises a semiconductor wafer carrier wherein conductive dopants are implanted into the carrier in order to amplify the coulombic forces between an electrostatic chuck and the carrier to compensate for reduced forces that result from thinner semiconductor wafers. Another embodiment forms conductive layers and vias within the carrier instead of implanting conductive dopants.

Abstract: Ti and TiN layers are formed on an integrated circuit substrate using a titanium target in non-nitrided mode in a hollow cathode magnetron apparatus. Neither a collimator nor a shield is used. Ti and TiN layers are deposited in vias and trenches having aspect ratios up to 5:1.