Abstract: This invention relates to a method and circuit for addressing a symmetric or asymmetric 2.sup.M -element DRAM module using identical circuitry. The method consists of receiving an original address comprising M bits 0 to M-1 identifying a specific memory element, then deriving from these bits a column address and a row address which together identify the specific memory element. The column address comprises N bits 0 to N-1 which match in direct order bits 0 to N-1 of the original address and the row address comprises N bits 0 to N-1 which match in reverse order bits N-2 to M-1 of the original address. A circuit for selectively connecting a set of input address lines to a set of output address lines in a column mapping or a row mapping is also disclosed. The circuit comprises M input address lines 0 to M-1 and N output address lines 0 to N-1.