Abstract: A circuit for detecting locking of a digital phase locked loop for locking the phase of a digital outgoing signal as provided by the loop to the phase of a digital incoming signal received by the loop, wherein the phase locked loop includes a detector for detecting the phase difference between the incoming signal and the outgoing signal, and the output signal from the phase difference detector has transitions of a first type in coincidence with transitions of a given type in the outgoing signal, and transitions of a second type in coincidence with transitions of a given type in the incoming signal, the circuit including locking detection means for detecting locking, the locking detection means themselves including means for sampling the output signal from the phase detector by those transitions in the outgoing signal that are of type opposite to the given type, means for storing groups of consecutive samples, comprising not less than three consecutive samples, and means for detecting the instant at which, for

Abstract: A method for controlling the operating mode of a digital phase-locked loop including a counter controlling incrementing or decrementing of the frequency of a digital clock signal internal to the loop is such that, the input signal of the loop being present intermittently, with random phase from one appearance to the next, the control method comprises, in this order, the following steps:detecting the appearance of the input signal,selecting a relatively low capacity of the counter to enable relatively fast synchronization of the loop,detecting synchronization of the loop,selecting a relatively high capacity of the counter to filter relatively strongly any phase variations of the input signal occurring while it is present, this latter adjustment being retained until the next detection of the appearance of the input signal.

Abstract: A wide-band transistorized amplifier including between two line couplers a cascade of stages of amplification and a negative feed-back quadripole connecting the output from the last stage of the cascade to the input to the first, and including a stage of correction by forward gain control, which is arranged in parallel across one of the stages of the cascade, which is connected to one of the couplers, characterized by the fact that the stage (10, 12) of the cascade, across which the correction stage is arranged in parallel, introduces a phase reversal, and that the correction stage includes a CE transistor (20, 20', 20") the base of which is connected on the one hand through an inductive phase-shift impedance (19, 19', 19") to the input to the said stage (10, 12) of the cascade, and on the other hand through a resistor (23, 23', 23") to the output from the said stage of the cascade, and the collector of which is connected through the putting in parallel of a resistor (21, 21', 21") and a capacitor (22, 22', 2