Abstract: This digital processing circuit or sequence includes means (10, 16) of sampling an analog signal and of converting the acquired samples into digital form, a shift register (25), means (23) of storing a value (N.sub..xi.) of an integration constant, a unit (30), an accumulator (31) and a sequencer (14) which controls the sampling and the conversion into digital form of the samples by the said means during a measuring period, the storage of the said digital value representing the last sample acquired in the shift register (25), the operation of the said unit (30) as an adder during the measuring period for the computation of a cumulative sum and, at the end of the said period, the operation of the unit (30) as a subtractor and the operations of rotation of the content of the accumulator (31) in order to divide the final result of the cumulative sum by the value (N.sub..xi.) of the integration constant.

Abstract: This interface enables the integrated circuit with which it is associated to be placed in a test configuration by applying to its test input terminal (2) a voltage higher than the power supply voltage (V.sub.cc) of the circuitry. In the rest state, the interface then supplies a low logic level to its output terminal (5). If the test command voltage is applied, this level changes state.The interface comprises, in particular, two transistors (M.sub.1, M.sub.2) of opposite types of conductivity which are fed by a constant current source (10, M.sub.5, M.sub.6). The interface switches over when the input transistor (M.sub.1) is put into the conducting state by the test command voltage so as to divert a fraction of the current flowing in the second transistor (M.sub.2).The input terminal (2) can at the same time be a functional input terminal of the integrated circuit.

Abstract: An output stage of a calculator (2) has a transfer function of the form: tc=N.TSD+.epsilon. where .epsilon. is a small and known quantity; t.sub.c is the conduction time of the coil, N is a number of angular fractions or periods of an interpolation signal; and TSD is the period corresponding to one tooth on the starter gear. The device comprises measurement means (1, 32, 36) for measuring the time strictly necessary to obtain the required energy; means (6, 9, 13, 17) for generating signals at each fraction of the angular marking signal in order to obtain a time measurement of a counting window and means (21, 25, 29) for counting and memorizing during this window an interpolation signal of the angular resolution n times higher.