Patents by Inventor Jean-Luc Nauleau

Jean-Luc Nauleau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9793240
    Abstract: An apparatus includes a wafer portion and a plurality of die fabricated in the wafer portion in a defined pattern such that the die are separated from each other by a dicing area or a street. The apparatus includes a conductive connection between given adjacent die. The conductive connection is electrically coupled to circuitry disposed on the given adjacent die.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: October 17, 2017
    Assignee: SILICON LABORATORIES INC.
    Inventors: Ka Y. Leung, Jean-Luc Nauleau
  • Publication number: 20150294954
    Abstract: An apparatus includes a wafer portion and a plurality of die fabricated in the wafer portion in a defined pattern such that the die are separated from each other by a dicing area or a street. The apparatus includes a conductive connection between given adjacent die. The conductive connection is electrically coupled to circuitry disposed on the given adjacent die.
    Type: Application
    Filed: October 31, 2014
    Publication date: October 15, 2015
    Inventors: KA Y. LEUNG, JEAN-LUC NAULEAU
  • Patent number: 8946868
    Abstract: A semiconductor wafer including a plurality of die fabricated therein in a defined pattern. They are separated from each other by a dicing area or street and at least a portion of adjacent die on the wafer include at least a conductive connection between given adjacent die that is electrically interfaced to circuitry disposed on the given adjacent die.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: February 3, 2015
    Assignee: Silicon Laboratories Inc.
    Inventors: Ka Y. Leung, Jean-Luc Nauleau
  • Patent number: 8041227
    Abstract: A communication device is disclosed having optical and near-field communication capability. The device includes an optical transceiver circuit fabricated on an integrated circuit die and configured to transmit and receive far field signals. A near field transceiver circuit is also fabricated on the integrated circuit die and is configured to transmit and receive near-field electro-magnetic signals. Control circuitry is provided to selectively enable the optical transceiver circuit and the near field transceiver circuit responsive to an external control signal.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: October 18, 2011
    Assignee: Silicon Laboratories Inc.
    Inventors: Wayne T. Holcombe, Pavel Konecny, Miroslav Svajda, Jean-Luc Nauleau, Robert Gordon Farmer
  • Publication number: 20110073996
    Abstract: A semiconductor wafer including a plurality of die fabricated therein in a defined pattern. They are separated from each other by a dicing area or street and at least a portion of adjacent die on the wafer include at least a conductive connection between given adjacent die that is electrically interfaced to circuitry disposed on the given adjacent die.
    Type: Application
    Filed: September 30, 2009
    Publication date: March 31, 2011
    Applicant: SILICON LABORATORIES INC.
    Inventors: KA Y. LEUNG, JEAN-LUC NAULEAU
  • Publication number: 20100021176
    Abstract: A communication device is disclosed having optical and near-field communication capability. The device includes an optical transceiver circuit fabricated on an integrated circuit die and configured to transmit and receive far field signals. A near field transceiver circuit is also fabricated on the integrated circuit die and is configured to transmit and receive near-field electro-magnetic signals. Control circuitry is provided to selectively enable the optical transceiver circuit and the near field transceiver circuit responsive to an external control signal.
    Type: Application
    Filed: November 15, 2007
    Publication date: January 28, 2010
    Applicant: Integration Associates Inc.
    Inventors: Wayne T. Holcombe, Pavel Konecny, Miroslav Svajda, Jean-Luc Nauleau, Robert Farmer
  • Patent number: 7164310
    Abstract: The present invention is directed toward a system and apparatus for digitally controlling a bias control signal for at least one transistor. The present invention provides for software writable registers that control the bias control signal. The present invention further provides for the bias control signal to be temperature compensated based upon a temperature signal and a temperature profile stored in software writable registers. The present invention further provides for software control of the initialization and configuration of the bias control signal through stored program control of the values in the software writable registers.
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: January 16, 2007
    Assignee: Integration Associates Inc.
    Inventors: Jean-Luc Nauleau, Janos Erdelyi, William H. McCalpin
  • Patent number: 6548878
    Abstract: A method is shown for producing a distributed PN photodiode having a first active region of the photodiode that can be made arbitrarily thin. A fabrication substrate is doped to have a first conductivity type in order to form the first active region of the photodiode. A layer can also be formed upon the first surface of the fabrication substrate or a first surface of a handling wafer, where the layer can be an oxide layer, where a thickness of the oxide layer can be controlled to form a dielectric refractive reflector, a reflective layer, or a conductive layer. The first surface of the handling substrate is bonded to the first surface of the fabrication substrate. A second surface of the fabrication is then lapped to a obtain a preselected thickness of the first active region. A plurality of second active regions of the photodiode having a second conductivity type is formed on the second surface of the fabrication substrate.
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: April 15, 2003
    Assignee: Integration Associates, Inc.
    Inventors: Jean-Luc Nauleau, Wayne T. Holcombe, Pierre Irissou