Abstract: According to one implementation of the present disclosure, a power grid comprising: one or more cells; a metal layer; first and second buried power rails; and one or more local interconnects, wherein one or more local interconnect stitches are configured to electrically couple the one or more cells to either of the first or second buried power rails through the metal layer and the one or more local interconnects.

Abstract: A computer-implemented method of generating a layout of a circuit block of an integrated circuit comprises: receiving input data defining a logical operation of the circuit block; accessing a cell library providing a plurality of candidate cells; determining, with reference to the input data, a set of cells to be used to implement the circuit block, the cells defining circuit elements for fabrication on a substrate; and generating the layout by employing a place and route tool to determine a placement of the set of cells and performing a routing operation to interconnect interface terminals of the set of cells by determining routing paths to be provided within a plurality of metal layers including a lowest metal layer overlying the cells and within which interface terminals of the cells are provided and one or more further metal layers overlying the lowest metal layer; in which the step of determining routing paths comprises determining a routing path between interface terminals of a group of two or more cell

Abstract: A computer implemented method is described for generating a layout of a circuit block of an integrated circuit. The method comprises receiving input data defining a logical operation of the circuit block, and accessing a cell library providing a plurality of cells that define circuit elements, in order to determine with reference to the input data the cells to be used to implement the circuit block. A place and route tool is then employed to generate the layout by determining a placement of the determined cells and performing a routing operation to determine routing paths to be provided within a plurality of metal layers in order to interconnect the determined cells. The cell library provides cells that define in at least one metal layer one or more superfluous metal sections that are required to comply with design rules but which are unused by the cell.

Abstract: A computer-implemented method of generating a layout of a circuit block of an integrated circuit comprises: receiving input data defining a logical operation of the circuit block; accessing a cell library providing a plurality of candidate cells; determining, with reference to the input data, a set of cells to be used to implement the circuit block, the cells defining circuit elements for fabrication on a substrate; and generating the layout by employing a place and route tool to determine a placement of the set of cells and performing a routing operation to interconnect interface terminals of the set of cells by determining routing paths to be provided within a plurality of metal layers including a lowest metal layer overlying the cells and within which interface terminals of the cells are provided and one or more further metal layers overlying the lowest metal layer; in which the step of determining routing paths comprises determining a routing path between interface terminals of a group of two or more cell

Abstract: A computer implemented method is described for generating a layout of a circuit block of an integrated circuit. The method comprises receiving input data defining a logical operation of the circuit block, and accessing a cell library providing a plurality of cells that define circuit elements, in order to determine with reference to the input data the cells to be used to implement the circuit block. A place and route tool is then employed to generate the layout by determining a placement of the determined cells and performing a routing operation to determine routing paths to be provided within a plurality of metal layers in order to interconnect the determined cells. The cell library provides cells that define in at least one metal layer one or more superfluous metal sections that are required to comply with design rules but which are unused by the cell.

Abstract: Various implementations described herein are directed to an integrated circuit with mitigated resistance. The integrated circuit may include a cell having a plurality of transistors including a first transistor of a first type and a second transistor of a second type that is different from the first type. The integrated circuit may include a first wire coupling the first transistor to the second transistor. The integrated circuit may include a second wire coupling the first wire to an output routing wire. The integrated circuit may include a redundant wire further coupling the first wire to the output routing wire.

Abstract: Various implementations described herein are directed to a system and methods for generating timing data for an integrated circuit. In one implementation, the method may include generating first timing data for the integrated circuit, and the first timing data may be related to one or more variations of operating conditions for the integrated circuit. Further, the method may include extracting parameter values from the first timing data in association with the one or more variations of operating conditions. Further, the method may include generating second timing data for the integrated circuit, and the second timing data may be based on the extracted parameter values.

Abstract: Various implementations described herein are directed to an integrated circuit with mitigated resistance. The integrated circuit may include a cell having a plurality of transistors including a first transistor of a first type and a second transistor of a second type that is different from the first type. The integrated circuit may include a first wire coupling the first transistor to the second transistor. The integrated circuit may include a second wire coupling the first wire to an output routing wire. The integrated circuit may include a redundant wire further coupling the first wire to the output routing wire.

Abstract: Various implementations described herein are directed to a system and methods for generating timing data for an integrated circuit. In one implementation, the method may include generating first timing data for the integrated circuit, and the first timing data may be related to one or more variations of operating conditions for the integrated circuit. Further, the method may include extracting parameter values from the first timing data in association with the one or more variations of operating conditions. Further, the method may include generating second timing data for the integrated circuit, and the second timing data may be based on the extracted parameter values.

Abstract: A method of generating an integrated circuit layout comprises a step of determining a placement of standard cells selected from a standard cell library while permitting boundary conflicts in which incompatible boundary regions of standard cells are placed next to each other. After determining routing connections between the standard cells, the integrated circuit layout is generated. The generation of the integrated circuit layout includes a mapping step of mapping at least one incompatible boundary region to an alternative boundary region to resolve at least one boundary conflict.

Abstract: A method of performing and correcting a timing analysis performed by a data processing apparatus on a circuit formed of a plurality of cells to account for the reverse Miller effect. The timing analysis steps includes identifying cells on and in parallel with a signal path that are driven by a same signal and determining an output transition time and a delay using the characterization data for the cell. The correcting steps includes providing further characterization data for some of the cells; correcting the output transition time for some of the cells by increasing the output transition time by an amount dependent upon the Miller capacitance for the cell and using the correction to the output transition time to correct an input transition time for a next cell; and calculating a time taken for a data signal to travel along the signal path from the delay times.

Abstract: A method of performing and correcting a timing analysis performed by a data processing apparatus on a circuit formed of a plurality of cells to account for the reverse Miller effect. The timing analysis steps includes identifying cells on and in parallel with a signal path that are driven by a same signal and determining an output transition time and a delay using the characterisation data for the cell. The correcting steps includes providing further characterisation data for some of the cells; correcting the output transition time for some of the cells by increasing the output transition time by an amount dependent upon the Miller capacitance for the cell and using the correction to the output transition time to correct an input transition time for a next cell; and calculating a time taken for a data signal to travel along the signal path from the delay times.

Abstract: A method of adapting a layout of a standard cell of an integrated circuit is provided. A current collection path in the standard cell is selected which connects components within the standard cell to an output connection, wherein the current collection path is arranged to collect current from the components at a plurality of current collection points arranged along its length. A maximum current location on the current collection path is determined at which a maximum possible current flow in the current collection path will occur if the output connection is connected there, the maximum possible current flow being a sum of current contributions from the current collection points. A maximum width of the current collection path at the maximum current location is determined such that the maximum width satisfies a minimum path width requirement with respect to the maximum possible current flow.

Abstract: A circuit comprising a plurality of semiconductor inverting devices arranged in series is disclosed. Each of the semiconductor inverting devices comprise at least one NMOS transistor and at least one PMOS transistor and alternate ones of the inverting devices in the series comprise transistors having a first ratio of a width of the at least one PMOS transistor and the at least one NMOS transistor; and alternate ones of said inverting devices in the series comprise transistors having a second ratio of a width of the at least one PMOS transistor and the at least one NMOS transistor; wherein the first ratio and the second ratio are not equal and in some case, the first and second ratios are such that a sum of a delay in a rise time of a signal propagated by a first inverting device and a fall time of a signal propagated by a second inverting device is substantially equal to a delay in a fall time of a signal propagated by the first inverting device.

Abstract: A method of adapting a layout of a standard cell of an integrated circuit is provided. A current collection path in the standard cell is selected which connects components within the standard cell to an output connection, wherein the current collection path is arranged to collect current from the components at a plurality of current collection points arranged along its length. A maximum current location on the current collection path is determined at which a maximum possible current flow in the current collection path will occur if the output connection is connected there, the maximum possible current flow being a sum of current contributions from the current collection points. A maximum width of the current collection path at the maximum current location is determined such that the maximum width satisfies a minimum path width requirement with respect to the maximum possible current flow.

Abstract: A decoupling capacitor is disclosed that has an n-type portion and a p-type portion in a semiconductor. The decoupling capacitor is formed of an NFET transistor and a PFET transistor, the PFET transistor being substantially formed in the n-type portion and the NFET transistor being substantially formed in the p-type portion, a boundary between the n-type portion and the p-type portion being substantially straight. The transistors are arranged such that a source and drain of the PFET transistor are connected to a high voltage rail and a source and drain of the NFET transistor are connected to a low voltage rail.

Abstract: A circuit comprising a plurality of semiconductor inverting devices arranged in series is disclosed. Each of the semiconductor inverting devices comprise at least one NMOS transistor and at least one PMOS transistor and alternate ones of the inverting devices in the series comprise transistors having a first ratio of a width of the at least one PMOS transistor and the at least one NMOS transistor; and alternate ones of said inverting devices in the series comprise transistors having a second ratio of a width of the at least one PMOS transistor and the at least one NMOS transistor; wherein the first ratio and the second ratio are not equal and in some case, the first and second ratios are such that a sum of a delay in a rise time of a signal propagated by a first inverting device and a fall time of a signal propagated by a second inverting device is substantially equal to a delay in a fall time of a signal propagated by the first inverting device.

Abstract: A decoupling capacitor is disclosed that has an n-type portion and a p-type portion in a semiconductor, said decoupling capacitor comprising an NFET transistor and a PFET transistor, said PFET transistor being substantially formed in said n-type portion and said NFET transistor being substantially formed in said p-type portion, a boundary between said n-type portion and said p-type portion being substantially straight, said transistors being arranged such that a source and drain of said PFET transistor are connected to a high voltage rail and a source and drain of said NFET transistor are connected to a low voltage rail.

Abstract: The invention concerns a semi-conductor device comprising on a substrate: a first dynamic threshold voltage MOS transistor (10), with a gate (116), and a channel (111) of a first conductivity type, and a current limiter means (20) connected between the gate and the channel of said first transistor. In accordance with the invention, this first transistor is fitted with a first doped zone (160) of the first conductivity type, connected to the channel, and the current limiter means comprises a second doped zone (124) of a second conductivity type, placed against the first doped zone and electrically connected to the first zone by an ohmic connection. Application to the manufacture of CMOS circuits.

Abstract: A production of a capacitor includes the simultaneous production, in at least part of an intertrack insulating layer (3) associated with a given metallization level, on the one hand, of the two electrodes (50, 70) and of the dielectric layer (60) of the capacitor and, on the other hand, of a conducting trench (41) which laterally extends the lower electrode of the capacitor, is electrically isolated from the upper electrode and has a transverse dimension smaller than the transverse dimension of the capacitor, and the production, in the interlevel insulating layer (8) covering the intertrack insulating layer, of two conducting pads (80, 81) which come into contact with the upper electrode of the capacitor and with the conducting trench, respectively.