Patents by Inventor Jean-Luc Velut

Jean-Luc Velut has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10601722
    Abstract: The disclosure relates to a network interface controller for dynamically managing a retransmission delay of a message to resend the message if the retransmission delay is exceeded. The controller includes a communication module to receive an instruction for transmitting a message, said instruction including characteristic data of the message; transmission buffer memory to store the characteristic data and to associate it with a retransmission delay; a slowdown defining calculator to define a value of the division factor from said characteristic data; a reference clock to generate a fixed frequency signal; a frequency divider to generate a reduced frequency signal from the value of the division factor and the fixed frequency signal; and a reduced frequency clock associated with the transmission buffer memory to allow the retransmission delay to be timed from the reduced frequency signal and to trigger a retransmission of the message if the retransmission delay is exceeded.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: March 24, 2020
    Assignee: BULL SAS
    Inventors: Ghassan Chehaibar, Jean-Luc Velut
  • Publication number: 20190109796
    Abstract: The disclosure relates to a network interface controller for dynamically managing a retransmission delay of a message to resend the message if the retransmission delay is exceeded. The controller includes a communication module to receive an instruction for transmitting a message, said instruction including characteristic data of the message; transmission buffer memory to store the characteristic data and to associate it with a retransmission delay; a slowdown defining calculator to define a value of the division factor from said characteristic data; a reference clock to generate a fixed frequency signal; a frequency divider to generate a reduced frequency signal from the value of the division factor and the fixed frequency signal; and a reduced frequency clock associated with the transmission buffer memory to allow the retransmission delay to be timed from the reduced frequency signal and to trigger a retransmission of the message if the retransmission delay is exceeded.
    Type: Application
    Filed: October 10, 2018
    Publication date: April 11, 2019
    Inventors: Ghassan Chehaibar, Jean-Luc Velut