Abstract: The invention relates to a method for reading data from a semiconductor memory, said method comprising the following steps in this order: providing at least one first memory bank and at least one shadow memory bank which are each designed to store a multiplicity of binary data items, the same data as in the first memory bank being stored in the shadow memory bank; receiving a command for reading data which are to be read from the first memory bank; utilizing a state checking device of the semiconductor memory to check whether the first memory bank is in an open memory bank state, and, if the first memory bank is in the open memory bank state, reading the data which are to be read from the at least one shadow memory bank, and, if the first memory bank is not in the open memory bank state, reading the data which are to be read from the first memory bank, the open memory state being such a memory state of the memory bank which does not allow the data which are to be read to be read without previously closing an

Abstract: The present invention relates to a method for operating a semiconductor memory apparatus, comprising: transmitting a command instruction, particularly a write instruction and/or a read instruction, to the semiconductor memory apparatus; transmitting a data signal to and/or from the semiconductor memory apparatus; and transmitting a data clock signal is transmitted for the purpose of latching the data signal; wherein the preamble (P), which is the number of clock cycles between the first edge of the data clock signal (WQDS) and the first bit (D0) of the data signal (DQ), can be set. The invention also relates to a semiconductor memory system comprising a semiconductor memory apparatus and a processor unit configured to perform the method.

Abstract: The invention provides a semiconductor memory device that includes at least two memory banks. The semiconductor memory device is designed in such a way that: at least two processor units can carry out read accesses and write accesses to memory banks; and by means of an inhibit command communicated by one of the processor units, the write access by the processor unit which has communicated the inhibit command and/or by at least one of the other processor units to the inhibited memory bank is prevented at least occasionally. A circuit arrangement including the above semiconductor memory device is furthermore proposed.

Abstract: The invention relates to a method for reading data from a semiconductor memory, said method comprising the following steps in this order: providing at least one first memory bank and at least one shadow memory bank which are each designed to store a multiplicity of binary data items, the same data as in the first memory bank being stored in the shadow memory bank; receiving a command for reading data which are to be read from the first memory bank; utilizing a state checking device of the semiconductor memory to check whether the first memory bank is in an open memory bank state, and, if the first memory bank is in the open memory bank state, reading the data which are to be read from the at least one shadow memory bank, and, if the first memory bank is not in the open memory bank state, reading the data which are to be read from the first memory bank, the open memory state being such a memory state of the memory bank which does not allow the data which are to be read to be read without previously closing an

Abstract: Memory apparatus having a short word line cycle time and method for operating a memory apparatus. One embodiment provides a memory apparatus comprising at least one cell array having a multiplicity of memory cells, with each of the memory cells having an associated word line and an associated bit line; a control device which has a signaling connection to the word lines and to the bit lines and is configured to read data stored in the memory cells and to write data to the memory cells; wherein the control device is configured to execute a destructive read command (DRD) for reading data from at least one of the memory cells, comprising: electrically biasing a bit line associated with the at least one memory cell, opening a word line associated with the at least one memory cell, and destructively reading data stored in the at least one memory cell.

Abstract: The present invention relates to a method for operating a semiconductor memory apparatus, comprising: transmitting a command instruction, particularly a write instruction and/or a read instruction, to the semiconductor memory apparatus; transmitting a data signal to and/or from the semiconductor memory apparatus; and transmitting a data clock signal is transmitted for the purpose of latching the data signal; wherein the preamble (P), which is the number of clock cycles between the first edge of the data clock signal (WQDS) and the first bit (D0) of the data signal (DQ), can be set. The invention also relates to a semiconductor memory system comprising a semiconductor memory apparatus and a processor unit configured to perform the method.

Abstract: An integrated memory has at least two connection panels, which can be operated independently of one another, for external communication by the memory. In addition, a control circuit produces a number of first control signals and a number of second control signals for external tap-off. The number of first control signals corresponds to a number of memory banks. The first control signals are each associated with a memory bank and indicate that an associated memory bank is being accessed. The number of second control signals corresponds to the number of connection panels. One of the second control signals is produced if an access collision occurs between access to one of the memory banks via one connection panel and access to the same memory bank via another connection panel. Two processor units are connected to the connection panels and access the memory independently of one another on the basis of the control signals.

Abstract: The invention relates to a semiconductor memory apparatus and a method for operating a semiconductor memory apparatus which can be operated in a normal operating mode and in a self-refresh mode. The method comprises the following steps in the self-refresh mode: determining the operating temperature of the semiconductor memory apparatus; producing a temperature-dependent refresh signal, with a predetermined frequency value being associated with each operating temperature value; comparing the determined operating temperature with a first predetermined temperature value; and increasing the frequency of the refresh signal to a first predetermined frequency value when the determined operating temperature is less than or equal to the first predetermined temperature value.

Abstract: Semiconductor memory apparatus and methods of operating the same are provided. The apparatus has at least one first sense amplifier for amplifying a voltage level which has been read from a memory cell when the semiconductor memory apparatus is in an active operating mode and at least one second sense amplifier for amplifying a voltage level which has been read from the memory cell when the semiconductor memory apparatus is in a refresh operating mode. The apparatus is designed such that either the first or the second sense amplifier can be placed in electrical contact with the memory cell and the capacitance of the second sense amplifier is lower than the capacitance of the first sense amplifier.

Abstract: One embodiment of the invention provides a method for operating a semiconductor memory apparatus, comprising the following steps: providing a first timer signal; providing a second timer signal which is independent of the first timer signal; providing a data validation signal which can assume at least a first value and a second value, wherein the data validation signal assumes the first value when data transfer from and/or to the semiconductor memory apparatus is not taking place, and the data validation signal assumes the second value when data transfer from and/or to the semiconductor memory apparatus is taking place; transferring a write command to the semiconductor memory apparatus in sync with the first timer signal; in response to the received write command, setting the data validation signal to assume the second value; and reading-in data in sync with the second timer signal while the data validation signal is set to the second value.

Abstract: One embodiment of the invention provides a semiconductor memory apparatus comprising: a multiplicity of memory cells which are arranged in the manner of a matrix at least in regions, a multiplicity of address contacts for receiving a row address and/or column address for at least one memory cell, at least one address decoder for decoding the row and/or column addresses, and a descrambling device which is arranged in the electrical signal path between the address contacts and the address decoder. The descrambling device comprises address inputs for accepting input address bits of an input address which are received via the address contacts and address outputs for outputting output address bits of an output address to the address decoder. In a descrambling mode, the descrambling device is designed to allocate an output address bit explicitly to each input address bit of a received, scrambled row and/or column address such that the output address is the same as the unscrambled address.

Abstract: Semiconductor memory apparatus and methods of operating the same are provided. The apparatus has at least one first sense amplifier for amplifying a voltage level which has been read from a memory cell when the semiconductor memory apparatus is in an active operating mode and at least one second sense amplifier for amplifying a voltage level which has been read from the memory cell when the semiconductor memory apparatus is in a refresh operating mode. The apparatus is designed such that either the first or the second sense amplifier can be placed in electrical contact with the memory cell and the capacitance of the second sense amplifier is lower than the capacitance of the first sense amplifier.

Abstract: The invention provides a semiconductor memory device that includes at least two memory banks. The semiconductor memory device is designed in such a way that: at least two processor units can carry out read accesses and write accesses to memory banks; and by means of an inhibit command communicated by one of the processor units, the write access by the processor unit which has communicated the inhibit command and/or by at least one of the other processor units to the inhibited memory bank is prevented at least occasionally. A circuit arrangement including the above semiconductor memory device is furthermore proposed.

Abstract: A memory is provided which has a memory region for storing data, an input for receiving a data bundle with a plurality of temporally sequential data blocks and an input for receiving a data mask signal which is assigned to the data bundle. The memory also has a unit for receiving a data block from the plurality of temporally sequential data bundle data blocks which is to be written into the memory region in dependence on the data mask signal. The memory also includes a unit for writing the received data block into the memory region.

Abstract: Memory apparatus having a short word line cycle time and method for operating a memory apparatus. One embodiment provides a memory apparatus comprising at least one cell array having a multiplicity of memory cells, with each of the memory cells having an associated word line and an associated bit line; a control device which has a signaling connection to the word lines and to the bit lines and is configured to read data stored in the memory cells and to write data to the memory cells; wherein the control device is configured to execute a destructive read command (DRD) for reading data from at least one of the memory cells, comprising: electrically biasing a bit line associated with the at least one memory cell, opening a word line associated with the at least one memory cell, and destructively reading data stored in the at least one memory cell.

Abstract: The present invention is a random access memory device with a well-matched echo clock signal. The dynamic memory storage device includes a controller, a data bus and multiple memory modules. The data bus is coupled to the controller such that data read and data write information is transferred to and from the controller over the data bus. Multiple memory modules are coupled to the data bus and to the controller. Each of the memory module have a driver that produces an echo clock signal on an echo clock pin. The echo clock pin of each memory module is tied to each of the other memory modules and to the controller. In this way, during a read operation of the random access memory device the data bus and echo clock have matched loading conditions.

Abstract: A circuit configuration has a transmitter unit connected to a first signal line and a receiver unit connected to a second signal line and is coupled to the transmission unit via a third signal line and a control line. The transmission unit receives and transmits a first bit group to be transmitted and a subsequent, second bit group to be transmitted. The transmission unit respectively identifies a signal state change between bits in the transmitted first bit group and corresponding bits in the received second bit group and determines the number of signal state changes. On the basis of the number thereof, the transmission unit transmits the second bit group to the receiver unit in unaltered or altered form, with altered transmission being indicated by a control signal. By influencing the number of charge reversal operations during signal transmission, the circuit configuration permits an overall reduction in current drawn.

Abstract: In a semiconductor memory device, a printed circuit board connects a memory chip to an external circuit. The printed circuit board includes a multiplicity of pads arranged in a column. These pads connect the board to the memory chip. The board also includes a multiplicity of data terminals arranged in at least two columns and connected to the pads by data connections. The data connections are configured such that each data connection has essentially the same electrical properties as any other data connection.

Abstract: In order to operate an integrated dynamic memory having a memory cell array having bit lines and word lines a plurality of individual actions—to be performed for a memory access—from the activation of one of the word lines up to the precharging of the word lines are controlled in a synchronized manner with a clock signal. A value for defining a defined number of clock cycles between at least two individual actions is programmed at the beginning. For this purpose, a control circuit has a programmable unit. In this way, in conjunction with a clocked circuit, a comparatively high data throughput is made possible even at variable clock frequencies.

Abstract: The integrated memory chip has an external control terminal, a dynamic memory, and a control circuit for controlling a memory access to the dynamic memory. The control circuit is connected to the external control terminal, for receiving an access command indicating the beginning of a memory access. The control circuit further has an output, which is connected to the dynamic memory, for outputting at least one activation signal, read command or write command and precharge command generated from the access command. This makes it possible, in the case of use in a data processing system, to dispense with a DRAM controller provided outside the memory chip.