Patents by Inventor Jean-Marc Frailong

Jean-Marc Frailong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200314026
    Abstract: A network system for a data center is described in which an access node sprays a data flow of packets over a logical tunnel to another access node. In one example, a method comprises establishing, by a plurality of access nodes, a logical tunnel over a plurality of data paths across a switch fabric between a source access node and a destination access node included within the plurality of access nodes, wherein the source access node is coupled to a source network device; and spraying, by the source access node, a data flow of packets over the logical tunnel to the destination access node, wherein the source access node receives the data flow of packets from the source network device, and wherein spraying the data flow of packets includes directing each of the packets within the data flow to a least loaded data path.
    Type: Application
    Filed: June 15, 2020
    Publication date: October 1, 2020
    Inventors: Pradeep Sindhu, Deepak Goel, Jean-Marc Frailong, Srihari Raju Vegesna, Wael Noureddine, Philip A. Thomas, Satish D Deo, Sunil Mekad, Ayaskant Pani
  • Publication number: 20200280462
    Abstract: An access node that can be configured and optimized to perform input and output (I/O) tasks, such as storage and retrieval of data to and from network devices (such as solid state drives), networking, data processing, and the like. For example, the access node may be configured to receive data to be processed, wherein the access node includes a plurality of processing cores, a data network fabric, and a control network fabric; receive, over the control network fabric, a work unit message indicating a processing task to be performed a processing core; and process the work unit message, wherein processing the work unit message includes retrieving data associated with the work unit message over the data network fabric.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Inventors: Pradeep Sindhu, Jean-Marc Frailong, Bertrand Serlet, Wael Noureddine, Felix A. Marti, Deepak Goel, Paul Kim, Rajan Goyal, Aibing Zhou
  • Patent number: 10725825
    Abstract: A new processing architecture is described that utilizes a data processing unit (DPU). Unlike conventional compute models that are centered around a central processing unit (CPU), the DPU that is designed for a data-centric computing model in which the data processing tasks are centered around the DPU. The DPU may be viewed as a highly programmable, high-performance I/O and data-processing hub designed to aggregate and process network and storage I/O to and from other devices. The DPU comprises a network interface to connect to a network, one or more host interfaces to connect to one or more application processors or storage devices, and a multi-core processor with two or more processing cores executing a run-to-completion data plane operating system and one or more processing cores executing a multi-tasking control plane operating system. The data plane operating system is configured to support software functions for performing the data processing tasks.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: July 28, 2020
    Assignee: Fungible, Inc.
    Inventors: Pradeep Sindhu, Jean-Marc Frailong, Wael Noureddine, Felix A. Marti, Deepak Goel, Rajan Goyal, Bertrand Serlet
  • Patent number: 10721187
    Abstract: A system and method for routing network packets. A switch fabric connects a plurality of forwarding units, including an egress forwarding unit and two or more ingress forwarding units, each ingress forwarding unit forwarding network packets to the egress forwarding unit via the switch fabric. The egress forwarding unit includes a scheduler and an output queue. Each ingress forwarding unit includes a Virtual Output Queue (VOQ) connected to the output queue and a VOQ manager. The scheduler receives time of arrival information for network packets stored in the VOQs, determines, based on the time of arrival information for each network packet, a device resident time for the network packets stored in the VOQs, and requests, from one of the VOQs and based on the device resident times, the network packet with the longest device resident time.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: July 21, 2020
    Assignee: Juniper Networks, Inc.
    Inventors: Gary Goldman, Sarin Thomas, Jean-Marc Frailong, Harshad B Agashe
  • Patent number: 10686729
    Abstract: A network system for a data center is described in which a switch fabric provides full mesh interconnectivity such that any servers may communicate packet data to any other of the servers using any of a number of parallel data paths. Moreover, according to the techniques described herein, edge-positioned access nodes, optical permutation devices and core switches of the switch fabric may be configured and arranged in a way such that the parallel data paths provide single L2/L3 hop, full mesh interconnections between any pairwise combination of the access nodes, even in massive data centers having tens of thousands of servers.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: June 16, 2020
    Assignee: Fungible, Inc.
    Inventors: Pradeep Sindhu, Deepak Goel, Jean-Marc Frailong, Srihari Raju Vegesna, Wael Noureddine, Phillip A. Thomas, Satish Deo, Sunil Mekad, Ayaskant Pani
  • Publication number: 20200183841
    Abstract: Methods and apparatus for memory management are described. In one example, this disclosure describes a method that includes executing, by a first processing unit, first work unit operations specified by a first work unit message, wherein execution of the first work unit operations includes accessing data from shared memory included within the computing system, modifying the data, and storing the modified data in a first cache associated with the first processing unit; identifying, by the computing system, a second work unit message that specifies second work unit operations that access the shared memory; updating, by the computing system, the shared memory by storing the modified data in the shared memory; receiving, by the computing system, an indication that updating the shared memory with the modified data is complete; and enabling the second processing unit to execute the second work unit operations.
    Type: Application
    Filed: February 14, 2020
    Publication date: June 11, 2020
    Inventors: Wael Noureddine, Jean-Marc Frailong, Pradeep Sindhu, Bertrand Serlet
  • Patent number: 10659254
    Abstract: A highly-programmable access node is described that can be configured and optimized to perform input and output (I/O) tasks, such as storage and retrieval of data to and from storage devices (such as solid state drives), networking, data processing, and the like. For example, the access node may be configured to execute a large number of data I/O processing tasks relative to a number of instructions that are processed. The access node may be highly programmable such that the access node may expose hardware primitives for selecting and programmatically configuring data processing operations. As one example, the access node may be used to provide high-speed connectivity and I/O operations between and on behalf of computing devices and storage components of a network, such as for providing interconnectivity between those devices and a switch fabric of a data center.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: May 19, 2020
    Assignee: Fungible, Inc.
    Inventors: Pradeep Sindhu, Jean-Marc Frailong, Bertrand Serlet, Wael Noureddine, Felix A. Marti, Deepak Goel, Paul Kim, Rajan Goyal, Aibing Zhou
  • Publication number: 20200151101
    Abstract: Techniques are described in which a system having multiple processing units processes a series of work units in a processing pipeline, where some or all of the work units access or manipulate data stored in non-coherent memory. In one example, this disclosure describes a method that includes identifying, prior to completing processing of a first work unit with a processing unit of a processor having multiple processing units, a second work unit that is expected to be processed by the processing unit after the first work unit. The method also includes processing the first work unit, and prefetching, from non-coherent memory, data associated with the second work unit into a second cache segment of the buffer cache, wherein prefetching the data associated with the second work unit occurs concurrently with at least a portion of the processing of the first work unit by the processing unit.
    Type: Application
    Filed: January 17, 2020
    Publication date: May 14, 2020
    Inventors: Wael Noureddine, Jean-Marc Frailong, Felix A. Marti, Charles Edward Gray, Paul Kim
  • Publication number: 20200112524
    Abstract: In one embodiment, an apparatus includes a switch core that has a multi-stage switch fabric. A first set of peripheral processing devices coupled to the multi-stage switch fabric by a set of connections that have a protocol. Each peripheral processing device from the first set of peripheral processing devices is a storage node that has virtualized resources. The virtualized resources of the first set of peripheral processing devices collectively define a virtual storage resource interconnected by the switch core. A second set of peripheral processing devices coupled to the multi-stage switch fabric by a set of connections that have the protocol. Each peripheral processing device from the first set of peripheral processing devices is a compute node that has virtualized resources. The virtualized resources of the second set of peripheral processing devices collectively define a virtual compute resource interconnected by the switch core.
    Type: Application
    Filed: December 5, 2019
    Publication date: April 9, 2020
    Applicant: Juniper Networks, Inc.
    Inventors: Pradeep SINDHU, Gunes AYBAY, Jean-Marc FRAILONG, Anjan VENKATRAMANI, Quaizar VOHRA
  • Publication number: 20200092220
    Abstract: Timer management techniques are described. An example processing device includes a memory configured to store successive wheels available to be included in traversal paths for timers running on the device, each wheel representing a queue of timers, each wheel having a different, corresponding time delay (TO) value for queuing a timer, and processing circuitry in communication with the memory. The processing circuitry is configured to determine, in response to a request for a timer, a total traversal time for the timer, to select, from the stored wheels, a subset of wheels such that a sum of the respective TO values of the selected subset is within a predetermined margin of error with respect to the total traversal time for the timer, and to sequence the selected subset of wheels based on the respective TO values of the selected subset of wheels to form a traversal path for the timer.
    Type: Application
    Filed: September 12, 2019
    Publication date: March 19, 2020
    Inventors: Wael Noureddine, Jean-Marc Frailong
  • Patent number: 10565112
    Abstract: Methods and apparatus for memory management are described. In a disclosed embodiment, a system has a first and a second processor, with each processor able to access a memory system. A first work unit is received for execution by the first processor, with the memory system being accessed. A second work unit is generated for execution by a second processor upon execution of a first work unit. Only after the memory system is updated does processing of the second work unit by the second processor occur. This work unit message based ordering provides relay consistency for memory operations of multiple processors.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: February 18, 2020
    Assignee: Fungible, Inc.
    Inventors: Wael Noureddine, Jean-Marc Frailong, Pradeep Sindhu, Bertrand Serlet
  • Patent number: 10540288
    Abstract: Techniques are described in which a system having multiple processing units processes a series of work units in a processing pipeline, where some or all of the work units access or manipulate data stored in non-coherent memory. In one example, this disclosure describes a method that includes identifying, prior to completing processing of a first work unit with a processing unit of a processor having multiple processing units, a second work unit that is expected to be processed by the processing unit after the first work unit. The method also includes processing the first work unit, and prefetching, from non-coherent memory, data associated with the second work unit into a second cache segment of the buffer cache, wherein prefetching the data associated with the second work unit occurs concurrently with at least a portion of the processing of the first work unit by the processing unit.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: January 21, 2020
    Assignee: Fungible, Inc.
    Inventors: Wael Noureddine, Jean-Marc Frailong, Felix A. Marti, Charles Edward Gray, Paul Kim
  • Patent number: 10536400
    Abstract: In one embodiment, an apparatus includes a switch core that has a multi-stage switch fabric. A first set of peripheral processing devices coupled to the multi-stage switch fabric by a set of connections that have a protocol. Each peripheral processing device from the first set of peripheral processing devices is a storage node that has virtualized resources. The virtualized resources of the first set of peripheral processing devices collectively define a virtual storage resource interconnected by the switch core. A second set of peripheral processing devices coupled to the multi-stage switch fabric by a set of connections that have the protocol. Each peripheral processing device from the first set of peripheral processing devices is a compute node that has virtualized resources. The virtualized resources of the second set of peripheral processing devices collectively define a virtual compute resource interconnected by the switch core.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: January 14, 2020
    Assignee: Juniper Networks, Inc.
    Inventors: Pradeep Sindhu, Gunes Aybay, Jean-Marc Frailong, Anjan Venkatramani, Quaizar Vohra
  • Publication number: 20200014637
    Abstract: In one embodiment, edge devices can be configured to be coupled to a multi-stage switch fabric and peripheral processing devices. The edge devices and the multi-stage switch fabric can collectively define a single logical entity. A first edge device from the edge devices can be configured to be coupled to a first peripheral processing device from the peripheral processing devices. The second edge device from the edge devices can be configured to be coupled to a second peripheral processing device from the peripheral processing devices. The first edge device can be configured such that virtual resources including a first virtual resource can be defined at the first peripheral processing device. A network management module coupled to the edge devices and configured to provision the virtual resources such that the first virtual resource can be migrated from the first peripheral processing device to the second peripheral processing device.
    Type: Application
    Filed: September 18, 2019
    Publication date: January 9, 2020
    Applicant: Juniper Networks, Inc.
    Inventors: Pradeep SINDHU, Gunes AYBAY, Jean-Marc FRAILONG, Anjan VENKATRAMANI, Quaizar VOHRA
  • Patent number: 10454849
    Abstract: In one embodiment, edge devices can be configured to be coupled to a multi-stage switch fabric and peripheral processing devices. The edge devices and the multi-stage switch fabric can collectively define a single logical entity. A first edge device from the edge devices can be configured to be coupled to a first peripheral processing device from the peripheral processing devices. The second edge device from the edge devices can be configured to be coupled to a second peripheral processing device from the peripheral processing devices. The first edge device can be configured such that virtual resources including a first virtual resource can be defined at the first peripheral processing device. A network management module coupled to the edge devices and configured to provision the virtual resources such that the first virtual resource can be migrated from the first peripheral processing device to the second peripheral processing device.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: October 22, 2019
    Assignee: Juniper Networks, Inc.
    Inventors: Pradeep Sindhu, Gunes Aybay, Jean-Marc Frailong, Anjan Venkatramani, Quaizar Vohra
  • Publication number: 20190289102
    Abstract: Aspects of this disclosure describes techniques for parsing network packets, processing network packets, and modifying network packets before forwarding the modified network packets over a network. The present disclosure describes a system that, in some examples, parses network packets, generates data describing or specifying attributes of the network packet, identifies operations to be performed when processing a network packet, performs the identified operations, generates data describing or specifying how to modify and/or forward the network packet, modifies the network packet, and outputs the modified packet to another device or system, such as a switch.
    Type: Application
    Filed: March 13, 2019
    Publication date: September 19, 2019
    Inventors: Deepak Goel, Jean-Marc Frailong, Srihari Raju Vegesna, Stimit Kishor Oak, Rohit Sunkam Ramanujam, John David Huber, Hariharan Lakshminarayanan Thantry, Vikas Minglani, Saurin Patel, Sureshkumar Nedunchezhian
  • Publication number: 20190243765
    Abstract: Techniques are described in which a system having multiple processing units processes a series of work units in a processing pipeline, where some or all of the work units access or manipulate data stored in non-coherent memory. In one example, this disclosure describes a method that includes identifying, prior to completing processing of a first work unit with a processing unit of a processor having multiple processing units, a second work unit that is expected to be processed by the processing unit after the first work unit. The method also includes processing the first work unit, and prefetching, from non-coherent memory, data associated with the second work unit into a second cache segment of the buffer cache, wherein prefetching the data associated with the second work unit occurs concurrently with at least a portion of the processing of the first work unit by the processing unit.
    Type: Application
    Filed: April 10, 2018
    Publication date: August 8, 2019
    Inventors: Wael Noureddine, Jean-Marc Frailong, Felix A. Marti, Charles Edward Gray, Paul Kim
  • Publication number: 20190044888
    Abstract: In some embodiments, a non-transitory processor-readable medium stores code representing instructions to be executed by a processor. The code causes the processor to receive, at an edge device, a first data unit having a characteristic. The code causes the processor to identify, at a first time, an identifier of a service module associated with the characteristic in response to each entry from a set of entries within a flow table not being associated with the characteristic. The code causes the processor to define an entry in the flow table associated with the characteristic and the identifier of the service module. The code causes the processor to send the first data unit to the service module. The code causes the processor to receive, at the edge device, a second data unit having the characteristic, and send the second data unit to the service module based on the entry.
    Type: Application
    Filed: September 28, 2018
    Publication date: February 7, 2019
    Applicant: Juniper Networks, Inc.
    Inventors: Krishna NARAYANASWAMY, Jean-Marc FRAILONG, Anjan VENKATRAMANI, Srinivasan JAGANNADHAN
  • Publication number: 20190013965
    Abstract: A highly-programmable access node is described that can be configured and optimized to perform input and output (I/O) tasks, such as storage and retrieval of data to and from storage devices (such as solid state drives), networking, data processing, and the like. For example, the access node may be configured to execute a large number of data I/O processing tasks relative to a number of instructions that are processed. The access node may be highly programmable such that the access node may expose hardware primitives for selecting and programmatically configuring data processing operations. As one example, the access node may be used to provide high-speed connectivity and I/O operations between and on behalf of computing devices and storage components of a network, such as for providing interconnectivity between those devices and a switch fabric of a data center.
    Type: Application
    Filed: July 10, 2018
    Publication date: January 10, 2019
    Inventors: Pradeep Sindhu, Jean-Marc Frailong, Bertrand Serlet, Wael Noureddine, Felix A. Marti, Deepak Goel, Paul Kim, Rajan Goyal, Aibing Zhou
  • Publication number: 20190012350
    Abstract: A new processing architecture is described that utilizes a data processing unit (DPU). Unlike conventional compute models that are centered around a central processing unit (CPU), the DPU that is designed for a data-centric computing model in which the data processing tasks are centered around the DPU. The DPU may be viewed as a highly programmable, high-performance I/O and data-processing hub designed to aggregate and process network and storage I/O to and from other devices. The DPU comprises a network interface to connect to a network, one or more host interfaces to connect to one or more application processors or storage devices, and a multi-core processor with two or more processing cores executing a run-to-completion data plane operating system and one or more processing cores executing a multi-tasking control plane operating system. The data plane operating system is configured to support software functions for performing the data processing tasks.
    Type: Application
    Filed: July 10, 2018
    Publication date: January 10, 2019
    Inventors: Pradeep Sindhu, Jean-Marc Frailong, Wael Noureddine, Felix A. Marti, Deepak Goel, Rajan Goyal, Bertrand Serlet