Patents by Inventor Jean-Marc Frailong
Jean-Marc Frailong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240061713Abstract: A new processing architecture is described that utilizes a data processing unit (DPU). Unlike conventional compute models that are centered around a central processing unit (CPU), the DPU that is designed for a data-centric computing model in which the data processing tasks are centered around the DPU. The DPU may be viewed as a highly programmable, high-performance I/O and data-processing hub designed to aggregate and process network and storage I/O to and from other devices. The DPU comprises a network interface to connect to a network, one or more host interfaces to connect to one or more application processors or storage devices, and a multi-core processor with two or more processing cores executing a run-to-completion data plane operating system and one or more processing cores executing a multi-tasking control plane operating system. The data plane operating system is configured to support software functions for performing the data processing tasks.Type: ApplicationFiled: November 1, 2023Publication date: February 22, 2024Applicant: Microsoft Technology Licensing, LLCInventors: Pradeep Sindhu, Jean-Marc Frailong, Wael Noureddine, Felix A. Marti, Deepak Goel, Rajan Goyal, Bertrand Serlet
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Patent number: 11842216Abstract: A new processing architecture is described that utilizes a data processing unit (DPU). Unlike conventional compute models that are centered around a central processing unit (CPU), the DPU that is designed for a data-centric computing model in which the data processing tasks are centered around the DPU. The DPU may be viewed as a highly programmable, high-performance I/O and data-processing hub designed to aggregate and process network and storage I/O to and from other devices. The DPU comprises a network interface to connect to a network, one or more host interfaces to connect to one or more application processors or storage devices, and a multi-core processor with two or more processing cores executing a run-to-completion data plane operating system and one or more processing cores executing a multi-tasking control plane operating system. The data plane operating system is configured to support software functions for performing the data processing tasks.Type: GrantFiled: July 27, 2020Date of Patent: December 12, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Pradeep Sindhu, Jean-Marc Frailong, Wael Noureddine, Felix A. Marti, Deepak Goel, Rajan Goyal, Bertrand Serlet
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Publication number: 20230388222Abstract: A network system for a data center is described in which an access node sprays a data flow of packets over a logical tunnel to another access node. In one example, a method comprises establishing, by a plurality of access nodes, a logical tunnel over a plurality of data paths across a switch fabric between a source access node and a destination access node included within the plurality of access nodes, wherein the source access node is coupled to a source network device; and spraying, by the source access node, a data flow of packets over the logical tunnel to the destination access node, wherein the source access node receives the data flow of packets from the source network device, and wherein spraying the data flow of packets includes directing each of the packets within the data flow to a least loaded data path.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Applicant: Microsoft Technology Licensing, LLCInventors: Pradeep Sindhu, Deepak Goel, Jean-Marc Frailong, Srihari Raju Vegesna, Wael Noureddine, Philip A. Thomas, Satish Deo, Sunil Mekad, Ayaskant Pani
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Patent number: 11829295Abstract: Techniques are described in which a system having multiple processing units processes a series of work units in a processing pipeline, where some or all of the work units access or manipulate data stored in non-coherent memory. In one example, this disclosure describes a method that includes identifying, prior to completing processing of a first work unit with a processing unit of a processor having multiple processing units, a second work unit that is expected to be processed by the processing unit after the first work unit. The method also includes processing the first work unit, and prefetching, from non-coherent memory, data associated with the second work unit into a second cache segment of the buffer cache, wherein prefetching the data associated with the second work unit occurs concurrently with at least a portion of the processing of the first work unit by the processing unit.Type: GrantFiled: February 27, 2023Date of Patent: November 28, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Wael Noureddine, Jean-Marc Frailong, Felix A. Marti, Charles Edward Gray, Paul Kim
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Patent number: 11824683Abstract: A new processing architecture is described in which a data processing unit (DPU) is utilized within a device. Unlike conventional compute models that are centered around a central processing unit (CPU), example implementations described herein leverage a DPU that is specially designed and optimized for a data-centric computing model in which the data processing tasks are centered around, and the primary responsibility of, the DPU. For example, various data processing tasks, such as networking, security, and storage, as well as related work acceleration, distribution and scheduling, and other such tasks are the domain of the DPU. The DPU may be viewed as a highly programmable, high-performance input/output (I/O) and data-processing hub designed to aggregate and process network and storage I/O to and from multiple other components and/or devices. This frees resources of the CPU, if present, for computing-intensive tasks.Type: GrantFiled: March 29, 2022Date of Patent: November 21, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Pradeep Sindhu, Jean-Marc Frailong, Bertrand Serlet, Wael Noureddine, Felix A. Marti, Deepak Goel, Rajan Goyal
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Patent number: 11809321Abstract: Methods and apparatus for memory management are described. In one example, this disclosure describes a method that includes executing, by a first processing unit, first work unit operations specified by a first work unit message, wherein execution of the first work unit operations includes accessing data from shared memory included within the computing system, modifying the data, and storing the modified data in a first cache associated with the first processing unit; identifying, by the computing system, a second work unit message that specifies second work unit operations that access the shared memory; updating, by the computing system, the shared memory by storing the modified data in the shared memory; receiving, by the computing system, an indication that updating the shared memory with the modified data is complete; and enabling the second processing unit to execute the second work unit operations.Type: GrantFiled: June 10, 2022Date of Patent: November 7, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Wael Noureddine, Jean-Marc Frailong, Pradeep Sindhu, Bertrand Serlet
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Patent number: 11777839Abstract: A network system for a data center is described in which an access node sprays a data flow of packets over a logical tunnel to another access node. In one example, a method comprises establishing, by a plurality of access nodes, a logical tunnel over a plurality of data paths across a switch fabric between a source access node and a destination access node included within the plurality of access nodes, wherein the source access node is coupled to a source network device; and spraying, by the source access node, a data flow of packets over the logical tunnel to the destination access node, wherein the source access node receives the data flow of packets from the source network device, and wherein spraying the data flow of packets includes directing each of the packets within the data flow to a least loaded data path.Type: GrantFiled: June 15, 2020Date of Patent: October 3, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Pradeep Sindhu, Deepak Goel, Jean-Marc Frailong, Srihari Raju Vegesna, Wael Noureddine, Philip A. Thomas, Satish Deo, Sunil Mekad, Ayaskant Pani
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Patent number: 11734179Abstract: Techniques are described in which a system having multiple processing units processes a series of work units in a processing pipeline, where some or all of the work units access or manipulate data stored in non-coherent memory. In one example, this disclosure describes a method that includes identifying, prior to completing processing of a first work unit with a processing unit of a processor having multiple processing units, a second work unit that is expected to be processed by the processing unit after the first work unit. The method also includes processing the first work unit, and prefetching, from non-coherent memory, data associated with the second work unit into a second cache segment of the buffer cache, wherein prefetching the data associated with the second work unit occurs concurrently with at least a portion of the processing of the first work unit by the processing unit.Type: GrantFiled: June 28, 2021Date of Patent: August 22, 2023Assignee: Fungible, Inc.Inventors: Wael Noureddine, Jean-Marc Frailong, Felix A. Marti, Charles Edward Gray, Paul Kim
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Publication number: 20230231799Abstract: A network system for a data center. In one example, a method comprises establishing, by a plurality of access nodes, a logical tunnel over a plurality of data paths across a switch fabric between a source access node and a destination access node included within the plurality of access nodes, wherein the source access node is coupled to a source network device; and spraying, by the source access node, a data flow of packets over the logical tunnel to the destination access node, wherein the source access node receives the data flow of packets from the source network device, and wherein spraying the data flow of packets includes directing each of the packets within the data flow to one of the data paths based on an amount of data previously transmitted on each of the plurality of data paths.Type: ApplicationFiled: February 24, 2023Publication date: July 20, 2023Inventors: Pradeep Sindhu, Deepak Goel, Jean-Marc Frailong, Srihari Raju Vegesna, Wael Noureddine, Philip A. Thomas, Satish D Deo, Sunil Mekad, Ayaskant Pani
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Publication number: 20230205702Abstract: Techniques are described in which a system having multiple processing units processes a series of work units in a processing pipeline, where some or all of the work units access or manipulate data stored in non-coherent memory. In one example, this disclosure describes a method that includes identifying, prior to completing processing of a first work unit with a processing unit of a processor having multiple processing units, a second work unit that is expected to be processed by the processing unit after the first work unit. The method also includes processing the first work unit, and prefetching, from non-coherent memory, data associated with the second work unit into a second cache segment of the buffer cache, wherein prefetching the data associated with the second work unit occurs concurrently with at least a portion of the processing of the first work unit by the processing unit.Type: ApplicationFiled: February 27, 2023Publication date: June 29, 2023Inventors: Wael Noureddine, Jean-Marc Frailong, Felix A. Marti, Charles Edward Gray, Paul Kim
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Patent number: 11546189Abstract: An access node that can be configured and optimized to perform input and output (I/O) tasks, such as storage and retrieval of data to and from network devices (such as solid state drives), networking, data processing, and the like. For example, the access node may be configured to receive data to be processed, wherein the access node includes a plurality of processing cores, a data network fabric, and a control network fabric; receive, over the control network fabric, a work unit message indicating a processing task to be performed a processing core; and process the work unit message, wherein processing the work unit message includes retrieving data associated with the work unit message over the data network fabric.Type: GrantFiled: May 18, 2020Date of Patent: January 3, 2023Assignee: Fungible, Inc.Inventors: Pradeep Sindhu, Jean-Marc Frailong, Bertrand Serlet, Wael Noureddine, Felix A. Marti, Deepak Goel, Paul Kim, Rajan Goyal, Aibing Zhou
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Publication number: 20220300423Abstract: Methods and apparatus for memory management are described. In one example, this disclosure describes a method that includes executing, by a first processing unit, first work unit operations specified by a first work unit message, wherein execution of the first work unit operations includes accessing data from shared memory included within the computing system, modifying the data, and storing the modified data in a first cache associated with the first processing unit; identifying, by the computing system, a second work unit message that specifies second work unit operations that access the shared memory; updating, by the computing system, the shared memory by storing the modified data in the shared memory; receiving, by the computing system, an indication that updating the shared memory with the modified data is complete; and enabling the second processing unit to execute the second work unit operations.Type: ApplicationFiled: June 10, 2022Publication date: September 22, 2022Inventors: Wael Noureddine, Jean-Marc Frailong, Pradeep Sindhu, Bertrand Serlet
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Patent number: 11451491Abstract: In one embodiment, an apparatus includes a switch core that has a multi-stage switch fabric. A first set of peripheral processing devices coupled to the multi-stage switch fabric by a set of connections that have a protocol. Each peripheral processing device from the first set of peripheral processing devices is a storage node that has virtualized resources. The virtualized resources of the first set of peripheral processing devices collectively define a virtual storage resource interconnected by the switch core. A second set of peripheral processing devices coupled to the multi-stage switch fabric by a set of connections that have the protocol. Each peripheral processing device from the first set of peripheral processing devices is a compute node that has virtualized resources. The virtualized resources of the second set of peripheral processing devices collectively define a virtual compute resource interconnected by the switch core.Type: GrantFiled: December 5, 2019Date of Patent: September 20, 2022Assignee: Juniper Networks, Inc.Inventors: Pradeep Sindhu, Gunes Aybay, Jean-Marc Frailong, Anjan Venkatramani, Quaizar Vohra
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Publication number: 20220224564Abstract: A new processing architecture is described in which a data processing unit (DPU) is utilized within a device. Unlike conventional compute models that are centered around a central processing unit (CPU), example implementations described herein leverage a DPU that is specially designed and optimized for a data-centric computing model in which the data processing tasks are centered around, and the primary responsibility of, the DPU. For example, various data processing tasks, such as networking, security, and storage, as well as related work acceleration, distribution and scheduling, and other such tasks are the domain of the DPU. The DPU may be viewed as a highly programmable, high-performance input/output (I/O) and data-processing hub designed to aggregate and process network and storage I/O to and from multiple other components and/or devices. This frees resources of the CPU, if present, for computing-intensive tasks.Type: ApplicationFiled: March 29, 2022Publication date: July 14, 2022Inventors: Pradeep Sindhu, Jean-Marc Frailong, Bertrand Serlet, Wael Noureddine, Felix A. Marti, Deepak Goel, Rajan Goyal
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Patent number: 11360895Abstract: Methods and apparatus for memory management are described. In one example, this disclosure describes a method that includes executing, by a first processing unit, first work unit operations specified by a first work unit message, wherein execution of the first work unit operations includes accessing data from shared memory included within the computing system, modifying the data, and storing the modified data in a first cache associated with the first processing unit; identifying, by the computing system, a second work unit message that specifies second work unit operations that access the shared memory; updating, by the computing system, the shared memory by storing the modified data in the shared memory; receiving, by the computing system, an indication that updating the shared memory with the modified data is complete; and enabling the second processing unit to execute the second work unit operations.Type: GrantFiled: February 14, 2020Date of Patent: June 14, 2022Assignee: Fungible, Inc.Inventors: Wael Noureddine, Jean-Marc Frailong, Pradeep Sindhu, Bertrand Serlet
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Publication number: 20220150185Abstract: In one embodiment, edge devices can be configured to be coupled to a multi-stage switch fabric and peripheral processing devices. The edge devices and the multi-stage switch fabric can collectively define a single logical entity. A first edge device from the edge devices can be configured to be coupled to a first peripheral processing device from the peripheral processing devices. The second edge device from the edge devices can be configured to be coupled to a second peripheral processing device from the peripheral processing devices. The first edge device can be configured such that virtual resources including a first virtual resource can be defined at the first peripheral processing device. A network management module coupled to the edge devices and configured to provision the virtual resources such that the first virtual resource can be migrated from the first peripheral processing device to the second peripheral processing device.Type: ApplicationFiled: January 27, 2022Publication date: May 12, 2022Applicant: Juniper Networks, Inc.Inventors: Pradeep SINDHU, Gunes AYBAY, Jean-Marc FRAILONG, Anjan VENKATRAMANI, Quaizar VOHRA
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Patent number: 11303472Abstract: A new processing architecture is described in which a data processing unit (DPU) is utilized within a device. Unlike conventional compute models that are centered around a central processing unit (CPU), example implementations described herein leverage a DPU that is specially designed and optimized for a data-centric computing model in which the data processing tasks are centered around, and the primary responsibility of, the DPU. For example, various data processing tasks, such as networking, security, and storage, as well as related work acceleration, distribution and scheduling, and other such tasks are the domain of the DPU. The DPU may be viewed as a highly programmable, high-performance input/output (I/O) and data-processing hub designed to aggregate and process network and storage I/O to and from multiple other components and/or devices. This frees resources of the CPU, if present, for computing-intensive tasks.Type: GrantFiled: July 10, 2018Date of Patent: April 12, 2022Assignee: Fungible, Inc.Inventors: Pradeep Sindhu, Jean-Marc Frailong, Bertrand Serlet, Wael Noureddine, Felix A. Marti, Deepak Goel, Rajan Goyal
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Patent number: 11290395Abstract: A system and method for routing network packets. A switch fabric connects a plurality of forwarding units, including an egress forwarding unit and two or more ingress forwarding units, each ingress forwarding unit forwarding network packets to the egress forwarding unit via the switch fabric. The egress forwarding unit includes a scheduler and an output queue. Each ingress forwarding unit includes a Virtual Output Queue (VOQ) connected to the output queue and a VOQ manager. The scheduler receives time of arrival information for packet groups stored in the VOQs, determines, based on the time of arrival information for each packet group, a device resident time for each packet group, and discards the packet groups when the determined device resident time for the packet group is greater than a maximum resident time.Type: GrantFiled: July 20, 2020Date of Patent: March 29, 2022Assignee: Juniper Networks, Inc.Inventors: Gary Goldman, Sarin Thomas, Jean-Marc Frailong, Harshad B Agashe
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Patent number: 11271871Abstract: In one embodiment, edge devices can be configured to be coupled to a multi-stage switch fabric and peripheral processing devices. The edge devices and the multi-stage switch fabric can collectively define a single logical entity. A first edge device from the edge devices can be configured to be coupled to a first peripheral processing device from the peripheral processing devices. The second edge device from the edge devices can be configured to be coupled to a second peripheral processing device from the peripheral processing devices. The first edge device can be configured such that virtual resources including a first virtual resource can be defined at the first peripheral processing device. A network management module coupled to the edge devices and configured to provision the virtual resources such that the first virtual resource can be migrated from the first peripheral processing device to the second peripheral processing device.Type: GrantFiled: September 18, 2019Date of Patent: March 8, 2022Assignee: Juniper Networks, Inc.Inventors: Pradeep Sindhu, Gunes Aybay, Jean-Marc Frailong, Anjan Venkatramani, Quaizar Vohra
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Publication number: 20210349824Abstract: Techniques are described in which a system having multiple processing units processes a series of work units in a processing pipeline, where some or all of the work units access or manipulate data stored in non-coherent memory. In one example, this disclosure describes a method that includes identifying, prior to completing processing of a first work unit with a processing unit of a processor having multiple processing units, a second work unit that is expected to be processed by the processing unit after the first work unit. The method also includes processing the first work unit, and prefetching, from non-coherent memory, data associated with the second work unit into a second cache segment of the buffer cache, wherein prefetching the data associated with the second work unit occurs concurrently with at least a portion of the processing of the first work unit by the processing unit.Type: ApplicationFiled: June 28, 2021Publication date: November 11, 2021Inventors: Wael Noureddine, Jean-Marc Frailong, Felix A. Marti, Charles Edward Gray, Paul Kim