Patents by Inventor Jean-Marc Frailong

Jean-Marc Frailong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100061239
    Abstract: In one embodiment, a method includes sending a first flow control signal to a first stage of transmit queues when a receive queue is in a congestion state. The method also includes sending a second flow control signal to a second stage of transmit queues different from the first stage of transmit queues when the receive queue is in the congestion state.
    Type: Application
    Filed: September 30, 2008
    Publication date: March 11, 2010
    Inventors: Avanindra Godbole, Pradeep Sindhu, Jean-Marc Frailong
  • Publication number: 20100061241
    Abstract: In one embodiment, an apparatus includes a switch core that has a multi-stage switch fabric physically distributed among a set of chassis. The multi-stage switch fabric has a set of input buffers and a set of output ports. The switch core can be configured to be coupled to a set of edge devices. The apparatus can also include a controller implemented in hardware without software during operation and with software during configuration and monitoring. The controller can be coupled to the set of input buffers and the set of output ports. The controller can be configured to send a flow control signal to an input buffer from the set of input buffers when congestion at an output port from the set of output ports is predicted and before congestion in the switch core occurs.
    Type: Application
    Filed: June 30, 2009
    Publication date: March 11, 2010
    Inventors: Pradeep Sindhu, Gunes Aybay, Jean-Marc Frailong, Anjan Venkatramani, Quaizar Vohra
  • Publication number: 20100061238
    Abstract: In one embodiment, a method, comprising receiving at a receive side of a physical link a request to suspend transmission of data from a queue within a transmit side of a first stage of queues and to suspend transmission via a path including the physical link, a portion of the first stage of queues, and a portion of a second stage of queues. The method includes sending, in response to the request, a flow control signal to a flow control module configured to schedule transmission of the data from the queue within the transmit side of the first stage of queues. The flow control signal is associated with a first control loop including the path and differing from a second control loop that excludes the first stage of queues.
    Type: Application
    Filed: September 30, 2008
    Publication date: March 11, 2010
    Inventors: Avanindra Godbole, Pradeep Sindhu, Jean-Marc Frailong
  • Publication number: 20100061242
    Abstract: In one embodiment, edge devices can be configured to be coupled to a multi-stage switch fabric and peripheral processing devices. The edge devices and the multi-stage switch fabric can collectively define a single logical entity. A first edge device from the edge devices can be configured to be coupled to a first peripheral processing device from the peripheral processing devices. The second edge device from the edge devices can be configured to be coupled to a second peripheral processing device from the peripheral processing devices. The first edge device can be configured such that virtual resources including a first virtual resource can be defined at the first peripheral processing device. A network management module coupled to the edge devices and configured to provision the virtual resources such that the first virtual resource can be migrated from the first peripheral processing device to the second peripheral processing device.
    Type: Application
    Filed: September 11, 2009
    Publication date: March 11, 2010
    Inventors: Pradeep Sindhu, Gunes Aybay, Jean-Marc Frailong, Anjan Venkatramani, Quaizar Vohra
  • Publication number: 20100061390
    Abstract: In one embodiment, a processor-readable medium can store code representing instructions that when executed by a processor cause the processor to receive a value representing a congestion level of a receive queue and a value representing a state of a transmit queue. At least a portion of the transmit queue can be defined by a plurality of packets addressed to the receive queue. A rate value for the transmit queue can be defined based on the value representing the congestion level of the receive queue and the value representing the state of the transmit queue. The processor-readable medium can store code representing instructions that when executed by the processor cause the processor to define a suspension time value for the transmit queue based on the value representing the congestion level of the receive queue and the value representing the state of the transmit queue.
    Type: Application
    Filed: September 11, 2009
    Publication date: March 11, 2010
    Inventors: Avanindra GODBOLE, Arghajit Basu, Jean-Marc Frailong, Abhijeet Sampatrao Jadav, Naveen Jain, Pradeep Sindhu
  • Publication number: 20100061367
    Abstract: In one embodiment, an apparatus includes a switch core that defines a single logical entity and has a multi-stage switch fabric that has a set of stages physically distributed across a set of chassis. The set of stages collectively has a set of ingress ports and a set of egress ports. The switch core can be configured to be coupled to a set of peripheral processing devices via the set of ingress ports and the set of egress ports. The switch core can be configured to admit a set of cells associated with a packet into an ingress port from the set of ingress ports when delivery of the set of cells can be substantially guaranteed without loss through the multi-stage switch fabric.
    Type: Application
    Filed: June 30, 2009
    Publication date: March 11, 2010
    Inventors: Pradeep Sindhu, Gunes Aybay, Jean-Marc Frailong, Anjan Venkatramani, Quaizar Vohra
  • Publication number: 20100061391
    Abstract: In one embodiment, an apparatus can include a first edge device that can have a packet processing module. The first edge device can be configured to receive a packet. The packet processing module of the first edge device can be configured to produce cells based on the packet. A second edge device can have a packet processing module configured to reassemble the packet based on the cells. A multi-stage switch fabric can be coupled to the first edge device and the second edge device. The multi-stage switch fabric can define a single logical entity. The multi-stage switch fabric can have switch modules. Each switch module from the switch modules can have a shared memory device. The multi-stage switch fabric can be configured to switch the cells so that the cells are sent to the second edge device.
    Type: Application
    Filed: September 11, 2009
    Publication date: March 11, 2010
    Inventors: Pradeep Sindhu, Gunes Aybay, Jean-Marc Frailong, Anjan Venkatramani, Quaizar Vohra
  • Publication number: 20100061389
    Abstract: In one embodiment, an apparatus includes a switch core that has a multi-stage switch fabric. A first set of peripheral processing devices coupled to the multi-stage switch fabric by a set of connections that have a protocol. Each peripheral processing device from the first set of peripheral processing devices is a storage node that has virtualized resources. The virtualized resources of the first set of peripheral processing devices collectively define a virtual storage resource interconnected by the switch core. A second set of peripheral processing devices coupled to the multi-stage switch fabric by a set of connections that have the protocol. Each peripheral processing device from the first set of peripheral processing devices is a compute node that has virtualized resources. The virtualized resources of the second set of peripheral processing devices collectively define a virtual compute resource interconnected by the switch core.
    Type: Application
    Filed: June 30, 2009
    Publication date: March 11, 2010
    Inventors: Pradeep Sindhu, Gunes Aybay, Jean-Marc Frailong, Anjan Venkatramani, Quaizar Vohra
  • Publication number: 20100043067
    Abstract: A multicast-capable firewall allows firewall security policies to be applied to multicast traffic. The multicast-capable firewall may be integrated within a routing device, thus allowing a single device to provide both routing functionality, including multicast support, as well as firewall services. The routing device provides a user interface by which a user specifies one or more zones to be recognized by the integrated firewall when applying stateful firewall services to multicast packets. The user interface supports a syntax that allows the user to define subsets of the plurality of interfaces associated with the zones, and define a single multicast policy to be applied to multicast sessions associated with a multicast group. The multicast policy identifies common services to be applied pre-replication, and exceptions specifying additional services to be applied post-replication to copies of the multicast packets for the one or more zones.
    Type: Application
    Filed: April 29, 2009
    Publication date: February 18, 2010
    Applicant: Juniper Networks, Inc.
    Inventors: Kannan Varadhan, Jean-Marc Frailong, Anjan Venkatramani
  • Publication number: 20100002382
    Abstract: A front-to-back cooling system allows cooling of an apparatus containing two orthogonal sets of modules. Each set of modules is independently cooled. A vertical set of modules is cooled with vertical air flow across the modules that enters from a front of the apparatus and exhausts from a back of the apparatus. A horizontal set of modules is cooled with horizontal front-to-back air flow. When the horizontal set of modules is at the front of the apparatus, a plenum extending exterior to the vertical set of modules allows exhausting horizontally flowing air to the rear of the apparatus. When the horizontal set of modules is at the rear of the apparatus, a plenum extending exterior to the vertical set of modules allows moving air from the front of the apparatus to a chamber holding the horizontal modules.
    Type: Application
    Filed: July 3, 2008
    Publication date: January 7, 2010
    Applicant: Juniper Networks, Inc.
    Inventors: Gunes Aybay, Pradeep Sindhu, Jean-Marc Frailong, David J. Lima
  • Patent number: 7512080
    Abstract: Principles of the invention are directed to techniques for allowing a router forwarding packets within a computer network to perform two or more forwarding tree decisions per memory access. The router may implement forwarding information in the form of a radix tree having a number of nodes, and received packets may contain keys identifying a packet destination. The router may traverse the tree by testing two or more path control bits within the key per each of the traversed nodes. The values of the path control bits in the key determine the path traversed along the tree. The router also stores intermediate bit patterns at each node and tests intermediate bits in the key to determine whether a particular node is the best match to the routing prefix contained in the key, thereby eliminating a need to backtrack up the tree.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: March 31, 2009
    Assignee: Juniper Networks, Inc.
    Inventors: Kireeti Kompella, Jean Marc Frailong, Pradeep Sindhu
  • Patent number: 7406087
    Abstract: A network device includes an interface (105), a TCP/IP protocol fast processing path (115), and a TCP/IP protocol slow processing path (110). The interface (105) receives a packet and parses the packets to determine a characteristic of the packet. The TCP/IP protocol fast processing path (115) processes the packet if the characteristic of the packet includes a first characteristic. The TCP/IP protocol slow processing path (110) processes the packet if the characteristic of the packet includes a second characteristic.
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: July 29, 2008
    Assignee: Juniper Networks, Inc.
    Inventors: Nhon T. Quach, Ramesh Padmanabhan, Jean Marc Frailong
  • Patent number: 6557105
    Abstract: Embodiments of the present invention provide a cryptographic-based license management device comprising a license authority configured to generate a license in response to a product option request; an interface module having a plurality of product options that may be selectively enabled in response to a valid license issued by the license authority; a non-volatile memory associated with the interface module, the non-volatile memory module containing a programmable verification component for determining the authenticity of the license; and a license verification module associated with the interface module, the license verification module configured to verify the authenticity of a license using the programmable verification component contained within the non-volatile memory and enable selected product options provided the license is verified by the license verification module.
    Type: Grant
    Filed: April 14, 1999
    Date of Patent: April 29, 2003
    Assignee: Tut Systems, Inc.
    Inventors: Joseph John Tardo, Jean-Marc Frailong, Harold Lee Mendoza, Shiv Haris
  • Patent number: 6496858
    Abstract: The present invention discloses a initializing and reconfiguring a network interface device connecting a client computer system to an external network. The network interface device is configured for the client system by automated procedures and protocols initiated from a remote server. Software programs within the network interface device provide transparent communication between the client computer system and services available on the external network. Similar software programs and a configuration database within the network interface device provide transparent communication between the client computer system and the remote server.
    Type: Grant
    Filed: November 5, 1999
    Date of Patent: December 17, 2002
    Assignee: Tut Systems, Inc.
    Inventors: Jean-Marc Frailong, Charles A. Price, Joseph John Tardo
  • Patent number: 6230194
    Abstract: The present invention discloses a system for upgrading the software contents of a network interface device connecting a client computer system to an external network. The network interface device is configured for the client system by automated procedures and protocols initiated from a remote server. Software programs within the network interface device provide transparent communication between the client computer system and services available on the external network. Similar software programs and a configuration database within the network interface device provide transparent communication between the client computer system and the remote server.
    Type: Grant
    Filed: July 14, 1997
    Date of Patent: May 8, 2001
    Assignee: Freegate Corporation
    Inventors: Jean-Marc Frailong, Charles A. Price, Joseph John Tardo
  • Patent number: 6175650
    Abstract: Pixel blocks of an input image are type classified based on an analysis of the secord differences between the values of neighboring pixels in the rows and columns of each pixel block.
    Type: Grant
    Filed: January 26, 1998
    Date of Patent: January 16, 2001
    Assignee: Xerox Corporation
    Inventors: Pradeep S. Sindhu, Jean-Marc Frailong, Donald J. Curry, Asghar Nafarieh, Doron Kletter
  • Patent number: 6073172
    Abstract: The present invention discloses a initializing and reconfiguring a network interface device connecting a client computer system to an external network. The network interface device is configured for the client system by automated procedures and protocols initiated from a remote server. Software programs within the network interface device provide transparent communication between the client computer system and services available on the external network. Similar software programs and a configuration database within the network interface device provide transparent communication between the client computer system and the remote server.
    Type: Grant
    Filed: July 14, 1997
    Date of Patent: June 6, 2000
    Assignee: Freegate Corporation
    Inventors: Jean-Marc Frailong, Charles A. Price, Joseph John Tardo
  • Patent number: 6012100
    Abstract: The present invention discloses a network interface device for connecting a client computer system to an external network. The network interface device is configured for the client system by automated procedures and protocols initiated from a remote server. Software programs within the network interface device provide transparent communication between the client computer system and services available on the external network. Similar software programs and a configuration database within the network interface device provide transparent communication between the client computer system and the remote server.
    Type: Grant
    Filed: July 14, 1997
    Date of Patent: January 4, 2000
    Assignee: Freegate Corporation
    Inventors: Jean-Marc Frailong, Charles McManis, Charles A. Price, Mark James Herbert, Jean Antoine Gastinel, Joseph John Tardo
  • Patent number: 5924119
    Abstract: A shared memory multiprocessor having a packet switched bus for transferring data between a plurality processors, I/O devices, cache memories and main memory employs a bus protocol which permits multiple copies of data to be updated under the control of different processors while still ensuring that all processors and all I/O devices have access to consistent values for all data at all times.
    Type: Grant
    Filed: January 27, 1994
    Date of Patent: July 13, 1999
    Assignee: Xerox Corporation
    Inventors: Pradeep S. Sindhu, Jean-Marc Frailong, Jean A. Gastinel
  • Patent number: 5497480
    Abstract: A method and apparatus for removing a page table entry from a plurality of translation lookaside buffers ("TLBs") in a multiprocessor computer system. The multiprocessor computer system includes at least two processors coupled to a packet-switched bus. Page table entries are removed from a plurality of TLBs in the multiprocessor computer system by first broadcasting a demap request packet on the packet-switched bus in response to one of the processors requesting that a page table entry be removed from its associated TLB. The demap request packet includes a virtual address and context information specifying this page table entry. Controllers reply to the demap request packet by sending a first reply packet to the controller that sent the original demap request packet to indicate receipt of the demap request packet.
    Type: Grant
    Filed: July 29, 1994
    Date of Patent: March 5, 1996
    Assignees: Sun Microsystems, Inc., Xerox Corporation
    Inventors: Norman M. Hayes, Pradeep Sindhu, Jean-Marc Frailong, Sunil Nanda