Abstract: The present invention relates to fermented beverages and methods of making the same.

Abstract: A processing method in a convolutional neural network accelerator includes an array of unitary processing blocks associated with a set of respective local memories and performing computing operations on data stored in its local memories, wherein: during respective processing cycles, some unitary blocks receive and/or transmit data from or to neighbouring unitary blocks in at least one direction selected, on the basis of the data, from among the vertical and horizontal directions in the array; during the same cycles, some unitary blocks perform a computing operation in relation to data stored in their local memories during at least one previous processing cycle.

Abstract: A circuit comprises a series of calculating blocks that can each implement a group of neurons; a transformation block that is linked to the calculating blocks by a communication means and that can be linked at the input of the circuit to an external data bus, the transformation block transforming the format of the input data and transmitting the data to said calculating blocks by means of K independent communication channels, an input data word being cut up into sub-words such that the sub-words are transmitted over multiple successive communication cycles, one sub-word being transmitted per communication cycle over a communication channel dedicated to the word such that the N channels can transmit K words in parallel.

Abstract: The electronic architecture carries out the management of the functions of a vehicle, the functions being implemented via a set of sensors and actuators, the architecture comprising at least: a central computer; a real-time communication network; a set of interface modules, each module: aggregating signals from at least one of the sensors and sending the signals to the central computer via the communication network; and/or distributing control signals to at least one of the actuators; the central computer driving the actuators according to the signals from the sensors, the control signals for the actuators being sent to the interface modules via the communication network.

Abstract: A neuron circuit is capable of producing a weighted sum of digitized input signals and applying an activation function to the weighted sum so as to produce a digitized activation signal as output. The circuit includes at least: one multiplier multiplying each input signal (x1 to xn) with a weight value (w1j to wnj), one accumulator accumulating the results of the multiplier so as to produce the weighted sum, and one activation unit executing the activation function. The activation unit comprises at least one shift unit and at least one saturation unit capable of approximating a non-linear activation function. The result of the approximated activation function is obtained by one or more arithmetic shifts applied to the weighted sum.

Abstract: An implementation of neural networks on silicon for the processing of various signals comprises multidimensional signals such as images. The efficient implementation on silicon of a complete processing chain for the signal via the approach using neural networks is provided. The circuit comprises at least: a series of neuro-blocks grouped together in branches composed of a group of neuro-blocks and a broadcasting bus, the neuro-blocks connected to the broadcasting bus; a routing unit connected to the broadcasting bus of the branches, carrying out the routing and broadcasting of data to and from the branches; a transformation module connected to the routing unit via an internal bus and designed to be connected at the input of the circuit to an external databus, the module carrying out the transformation of input data into serial coded data. The processing operations internal to the circuit are carried out according to a serial communications protocol.

Abstract: A signal processing module comprises at least one operational unit incorporating computation units, input and output interfaces able to be linked to a bus and a memory storing data destined for the computation units, the memory being organized so that each data word is stored column-wise over several addresses according to an order dependent on the application, a column having a width of one bit, the words being transferred in series to the computation units.

Abstract: The present invention relates to a method to lighten the texture of a fermented dairy product comprising the following successive steps of: (a) providing a fermented dairy product containing 0.001 to 8 wt % of a texturizing agent and having a solid content comprised between 9.5 and 42 wt % and a total protein content comprised between 2.5 and 25 wt %, (b) freezing the said fermented dairy product at a temperature below 0° C. to obtain a frozen fermented dairy product, and (c) thawing the said frozen fermented dairy product at a temperature comprised between 0° C. and 10° C. to obtain a refrigerated fermented dairy product with a lightened texture.

Abstract: A circuit comprises a series of calculating blocks that can each implement a group of neurons; a transformation block that is linked to the calculating blocks by a communication means and that can be linked at the input of the circuit to an external data bus, the transformation block transforming the format of the input data and transmitting the data to said calculating blocks by means of K independent communication channels, an input data word being cut up into sub-words such that the sub-words are transmitted over multiple successive communication cycles, one sub-word being transmitted per communication cycle over a communication channel dedicated to the word such that the N channels can transmit K words in parallel.

Abstract: A neuron circuit is capable of producing a weighted sum of digitized input signals and applying an activation function to the weighted sum so as to produce a digitized activation signal as output. The circuit includes at least: one multiplier multiplying each input signal (x1 to xn) with a weight value (w1j to wnj), one accumulator accumulating the results of the multiplier so as to produce the weighted sum, and one activation unit executing the activation function. The activation unit comprises at least one shift unit and at least one saturation unit capable of approximating a non-linear activation function. The result of the approximated activation function is obtained by one or more arithmetic shifts applied to the weighted sum.

Abstract: The invention relates to a process for making a composition comprising a high amount of whey protein. The process involves preparing a mass having a high amount of whey protein, and then mixing with an aqueous preparation comprising a poly saccharide. The composition obtained presents a modified, controlled texture.

Abstract: The present invention relates to a method to lighten the texture of a fermented dairy product comprising the following successive steps of: (a) providing a fermented dairy product containing 0.001 to 8 wt % of a texturizing agent and having a solid content comprised between 9.5 and 42 wt % and a total protein content comprised between 2.5 and 25 wt %, (b) freezing the said fermented dairy product at a temperature below 0° C. to obtain a frozen fermented dairy product, and (c) thawing the said frozen fermented dairy product at a temperature comprised between 0° C. and 10° C. to obtain a refrigerated fermented dairy product with a lightened texture.

Abstract: A signal processing module comprises at least one operational unit incorporating computation units, input and output interfaces able to be linked to a bus and a memory storing data destined for the computation units, the memory being organized so that each data word is stored column-wise over several addresses according to an order dependent on the application, a column having a width of one bit, the words being transferred in series to the computation units.

Abstract: An implementation of neural networks on silicon for the processing of various signals comprises multidimensional signals such as images. The efficient implementation on silicon of a complete processing chain for the signal via the approach using neural networks is provided. The circuit comprises at least: a series of neuro-blocks grouped together in branches composed of a group of neuro-blocks and a broadcasting bus, the neuro-blocks connected to the broadcasting bus; a routing unit connected to the broadcasting bus of the branches, carrying out the routing and broadcasting of data to and from the branches; a transformation module connected to the routing unit via an internal bus and designed to be connected at the input of the circuit to an external databus, the module carrying out the transformation of input data into serial coded data. The processing operations internal to the circuit are carried out according to a serial communications protocol.

Abstract: The present disclosure relates to packaged long shelf life edible products, in particular dairy products, comprising tamarind extract, neb neb extract and weak organic acids. These packaged long shelf life edible products can be stored during at least 12 months under conditions of high temperature and high humidity level. The present disclosure also describes the manufacturing process for making the same.

Abstract: A method for preparing a frozen dessert includes the following steps: (a) adding onto a frozen composition contained in a vessel at least one additional powdery composition and/or from 3 to 18 wt % relative to frozen composition weight, of at least one additional liquid composition, the additional compositions containing not only sugar optionally mixed with water but also providing at least one nutritional benefit, in order to obtain a frozen composition with added liquid and/or powder; (b) placing the vessel containing the frozen composition with added liquid and/or powder in a texturizing device with grinding elements and optionally aeration elements; and (c) texturing the frozen composition with added liquid and/or powder in the texturing device.

Abstract: A process for the manufacture of a frozen dessert, includes the successive steps of: (a) freezing a mixture containing a fruit puree and/or juice, yoghurt and optionally added sugars and/or other ingredients, in order to obtain a frozen composition, (b) optionally bringing the frozen composition to a core temperature ranging from ?15 to ?25° C. or from ?15 to ?300° C., (c) placing the frozen composition in a device equipped with grinding elements and optionally with aerating elements, which device does not include extrusion members, and (d) texturing the frozen composition with the aid of the grinding and optionally aerating elements. It also relates to the frozen dessert thus obtained.

Abstract: A process is provided for the manufacture of a frozen dessert, comprising the successive steps consisting in: freezing an industrial milk composition comprising from 6 to 45% by weight of dry matter and fermented or nonfermented milk, the said composition not comprising both yoghurt and a fruit puree and/or juice, in order to obtain a frozen composition; optionally bringing the said frozen composition to a core temperature ranging from ?15 to ?25° C. or from ?15 to ?300 C, placing the said frozen composition in a device equipped with grinding means and optionally aerating means, and texturing the said frozen composition with the aid of the said grinding and optionally aerating means. It also relates to the frozen dessert thus obtained.

Abstract: A frozen composition based on yoghurt and fruit, containing: one or more fruits in pureed and/or juice form, representing from 30 to 49% or from 49.1 to 220% of the total weight of the composition, as fruit equivalent, from 51 to 70% by weight of yoghurt, and optionally one or more added sugars and/or other ingredients. A process for the manufacture of this composition, its use for the manufacture of a frozen dessert, and a process for the manufacture of the dessert, by grinding and optionally aerating the composition are also disclosed.

Abstract: An apparatus and method for using self-timing logic to make at least two accesses to a memory core in one clock cycle is disclosed. In one embodiment of the invention, a memory wrapper (28) incorporating self-timing logic (36) and a mux (32) is used to couple a single access memory core (30) to a memory interface unit (10). The memory interface unit (10) couples a central processing unit (12) to the memory wrapper (28). The self-timing architecture as applied to multi-access memory wrappers avoids the need for calibration. Moreover, the self-timing architecture provides for a full dissociation between the environment (what is clocked on the system clock) and the access to the core. A beneifical result of the invention is making access at the speed of the core while processing several access in one system clock cycle.