Abstract: A precision and high-speed analogue-to-digital converter has two separate groups of comparators linked by an intermediate network comprising a digital-to-analogue converter made up of current generators which are controlled by the logical outputs from the first group of comparators. These outputs represent the higher-order bits of the digital equivalent of the analogue input signal which is transmitted to the second group of comparators via a delay line. The digital-to-analogue converter causes a change in the threshold voltages applied to the comparators in the second group, which supply the lower-order digits of the coded input signal. The linking network further comprises means to compensate for errors at the inputs of the second group of comparators due to variations in the biasing currents of its comparators and also in the setting of their thresholds.